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61
Automated Pipeline Design
 38TH DESIGN AUTOMATION CONFERENCE (DAC ’01), JUNE, LAS VEGAS
, 2001
"... The interlock and forwarding logic is considered the tricky part of a fullyfeatured pipelined microprocessor and especially debugging these parts delays the hardware design process considerably. It is therefore desirable to automate the design of both interlock and forwarding logic. The hardware de ..."
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Cited by 18 (2 self)
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The interlock and forwarding logic is considered the tricky part of a fullyfeatured pipelined microprocessor and especially debugging these parts delays the hardware design process considerably. It is therefore desirable to automate the design of both interlock and forwarding logic. The hardware design engineer begins with a sequential implementation without any interlock and forwarding logic. A tool then adds the forwarding and interlock logic required for pipelining. This paper describes the algorithm for such a tool and the correctness is formally verified. We use a standard DLX RISC processor as an example.
Formal Verification of WordLevel Specifications
 Proc. Design Automation and Test in Europe (DATE
, 1999
"... Formal verification has become one of the most important steps in circuit design. In this context the verification of highlevel Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified ..."
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Cited by 13 (1 self)
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Formal verification has become one of the most important steps in circuit design. In this context the verification of highlevel Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on WordLevel Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn out to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach. 1
Equivalence Verification of Polynomial Datapaths with FixedSize BitVectors using Finite Ring Algebra
 in Intl. Conf. on ComputerAided Design, ICCAD
, 2005
"... Abstract — This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapathoriented designs that implement polynomial computations over fixedsize bitvectors. When the size (m) of the entire datapath is kept constant, fixedsize bitvector arithmetic manife ..."
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Cited by 13 (7 self)
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Abstract — This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapathoriented designs that implement polynomial computations over fixedsize bitvectors. When the size (m) of the entire datapath is kept constant, fixedsize bitvector arithmetic manifests itself as polynomial algebra over finite integer rings of residue classes m. The verification problem then reduces to that of checking Z2 equivalence of multivariate polynomials over Z2 m.Thispaper exploits the concepts of polynomial reducibility over Z2m and derives an algorithmic procedure to transform a given polynomial into a unique canonical form modulo 2 m. Equivalence testing is then carried out by coefficient matching. Experiments demonstrate the effectiveness of our approach over contemporary
Formal Verification of Designs with Complex Control by Symbolic Simulation
 Eds.): Correct Hardware Design and Verification Methods (CHARME ’99), LNCS 1703, September
, 1999
"... A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The verification tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decisiondiagram based techniques, with incr ..."
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Cited by 12 (3 self)
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A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The verification tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decisiondiagram based techniques, with increasing accuracy in order to optimize overall verification time without giving false negatives. The equivalence checker is able to cope with different numbers of control steps and different implementational details in the two descriptions to be compared.
Fast exact Toffoli network synthesis of reversible logic
 In Int’l Conf. on CAD
, 2007
"... Abstract—The research in the field of reversible logic is motivated by its application in lowpower design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of ge ..."
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Cited by 12 (10 self)
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Abstract—The research in the field of reversible logic is motivated by its application in lowpower design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that is based on Boolean Satisfiability. Furthermore, the principle limits of the original and the improved approach are shown. Then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. Experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude. I.
A.: On the complexity of fixedsize bitvector logics with binary encoded bitwidth
 In: Proc. SMT’12
, 2012
"... Bitprecise reasoning is important for many practical applications of Satisfiability Modulo Theories (SMT). In recent years efficient approaches for solving fixedsize bitvector formulas have been developed. From the theoretical point of view, only few results on the complexity of fixedsize bitve ..."
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Cited by 11 (5 self)
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Bitprecise reasoning is important for many practical applications of Satisfiability Modulo Theories (SMT). In recent years efficient approaches for solving fixedsize bitvector formulas have been developed. From the theoretical point of view, only few results on the complexity of fixedsize bitvector logics have been published. In this paper we show that some of these results only hold if unary encoding on the bitwidth of bitvectors is used. We then consider fixedsize bitvector logics with binary encoded bitwidth and establish new complexity results. Our proofs show that binary encoding adds more expressiveness to bitvector logics, e.g. it makes fixedsize bitvector logic even without uninterpreted functions nor quantification NExpTimecomplete. We also show that under certain restrictions the increase of complexity when using binary encoding can be avoided. 1
A Scalable Decision Procedure for FixedWidth BitVectors
 IN ICCAD
, 2009
"... Efficient decision procedures for bitvectors are essential for modern verification frameworks. This paper describes a new decision procedure for the core theory of bitvectors that exploits a reduction to equality reasoning. The procedure is embedded in a congruence closure algorithm, whose data st ..."
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Cited by 9 (1 self)
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Efficient decision procedures for bitvectors are essential for modern verification frameworks. This paper describes a new decision procedure for the core theory of bitvectors that exploits a reduction to equality reasoning. The procedure is embedded in a congruence closure algorithm, whose data structures are extended in order to efficiently manage the relations between bitvector slicings, modulo equivalence classes. The resulting procedure is incremental, backtrackable, and proof producing: it can be used as a theorysolver for a lazy SMT schema. Experiments show that our approach is comparable and often superior to bitblasting on the core fragment, and that it also helps as a theory layer when applied over the full bitvector theory.
Solving BitVector Equations
 Formal Methods in ComputerAided Design (FMCAD '98
, 1998
"... This paper is concerned with solving equations on fixed and nonfixed size bitvector terms. We define an equational transformation system for solving equations on terms where all sizes of bitvectors and extraction positions are known. This transformation system suggests a generalization for dealin ..."
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Cited by 9 (0 self)
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This paper is concerned with solving equations on fixed and nonfixed size bitvector terms. We define an equational transformation system for solving equations on terms where all sizes of bitvectors and extraction positions are known. This transformation system suggests a generalization for dealing with bitvectors of unknown size and unknown extraction positions. Both solvers adhere to the principle of splitting bitvectors only on demand, thereby making them quite effective in practice.
Automatic Verification of Arithmetic Circuits in RTL using Term Rewriting Systems
 In Accepted in IEEE Transactions on Computers
, 2003
"... for being my quest... for showing me the way... Acknowledgments I’d like to thank my advisor, Dr. Jacob Abraham for his invaluable support and guidance through the course of this work. His novel ideas, infectious enthusiasm and intellectually stimulating discussions kept me motivated and encouraged ..."
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Cited by 9 (3 self)
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for being my quest... for showing me the way... Acknowledgments I’d like to thank my advisor, Dr. Jacob Abraham for his invaluable support and guidance through the course of this work. His novel ideas, infectious enthusiasm and intellectually stimulating discussions kept me motivated and encouraged through the entire course of my Graduate Studies. Thank you Sir, for your firm belief in me. It kept me going in the most trying times. I’d also like to thank my colleague and fellow PhD student, Vinod Viswanath, for his support and assistance through my Masters. His experience, insight, resourcefulness, skills and alacrity have been a priceless source of inspiration and and help in obtaining this degree. Without his contribution, I don’t imagine I could have got this far. I’d like to thank Linda, Andrew, Shirley and Ruth for their promptness and efficiency in matters that required their attention. I’d also like to thank my labmates for their cooperation. I’d like to thank my friends Siddarth and Kunal, for bringing a lot of joy in my life in the U.S. Lastly, I’d like to thank my parents and sister for making me who I am. v
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing
, 2006
"... This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (such as ADD, MULT) over bitvectors with finite widths. A bitvector of size m represents integer values from 0 to 2 m −1; implying that the corresponding integer values are red ..."
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Cited by 7 (2 self)
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This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (such as ADD, MULT) over bitvectors with finite widths. A bitvector of size m represents integer values from 0 to 2 m −1; implying that the corresponding integer values are reduced modulo 2 m (%2 m). This suggests that bitvector arithmetic can be efficiently modeled as algebra over finite integer rings, where the bitvector size (m) dictates the cardinality of the ring (Z2m). This paper models the arithmetic datapath verification problem as equivalence testing of polynomial functions from Z2 n 1 × Z2 n 2 × · · · × Z2 n d → Z2 m. We formulate the equivalence problem f ≡ g into that of proving whether f − g ≡ 0%2 m. Fundamental concepts and results from number, ring and ideal theory are subsequently employed to develop systematic, complete algorithmic procedures to solve the problem. We demonstrate application of the proposed theoretical concepts to highlevel (behavioral/RTL) verification of bitvector arithmetic within practical CAD settings. Using our approach, we verify a set of arithmetic datapaths at RTL where contemporary verification approaches prove to be infeasible.