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19
Verification of an implementation of Tomasulo’s algorithm by compositional model checking
, 1998
"... Abstract. An implementation of an outoforder processing unit based on Tomasulo’s algorithm is formally verified using compositional model checking techniques. This demonstrates that finitestate methods can be applied to such algorithms, without recourse to higherorder proof systems. The paper in ..."
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Abstract. An implementation of an outoforder processing unit based on Tomasulo’s algorithm is formally verified using compositional model checking techniques. This demonstrates that finitestate methods can be applied to such algorithms, without recourse to higherorder proof systems. The paper introduces a novel compositional system that supports cyclic environment reasoning and multiple environment abstractions per signal. A proof of Tomasulo’s algorithm is outlined, based on refinement maps, and relying on the novel features of the compositional system. This proof is fully verified by the SMV verifier, using symmetry to reduce the number of assertions that must be verified. 1
An introduction to requirements capture using pvs: Specification of a simple autopilot
, 1996
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Experiments in Automating Hardware Verification using Inductive Proof Planning
, 1996
"... We present a new approach to automating the verification of hardware designs based on planning techniques. A database of methods is developed that combines tactics, which construct proofs, using specifications of their behaviour. Given a verification problem, a planner uses the method database to ..."
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Cited by 15 (8 self)
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We present a new approach to automating the verification of hardware designs based on planning techniques. A database of methods is developed that combines tactics, which construct proofs, using specifications of their behaviour. Given a verification problem, a planner uses the method database to build automatically a specialised tactic to solve the given problem. User interaction is limited to specifying circuits and their properties and, in some cases, suggesting lemmas. We have implemented our work in an extension of the Clam proof planning system. We report on this and its application to verifying a variety of combinational and synchronous sequential circuits including a parameterised multiplier design and a simple computer microprocessor.
FELIX: Using rewritinglogic for generating functionally equivalent implementations
 IN PROC. INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2005
, 2005
"... FELIX is a new design space exploration tool and graphical Integrated Development Environment (IDE) for the programming of coarsegrained reconfigurable architectures. Its main and novel advantage is the use of rewriting rules and logical strategies for the automated generation of alternative functi ..."
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Cited by 11 (8 self)
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FELIX is a new design space exploration tool and graphical Integrated Development Environment (IDE) for the programming of coarsegrained reconfigurable architectures. Its main and novel advantage is the use of rewriting rules and logical strategies for the automated generation of alternative functionally equivalent implementations from a single mathematical specification. The user selection of the rewriting logic strategies to be applied determines the resulting implementations, making it possible to quickly generate, simulate and evaluate alternative implementations that are logically equivalent. The FELIX System includes an interface to the KressArray Xplorer for hardware designspace exploration. The current version of the tool is targeted for the Pact eXtreme Processing Platform (XPP), with support for additional architectures planned in future versions.
The TLV System and its Applications
, 1996
"... Contents 1 Introduction 3 2 Background 6 2.1 Ordered Binary Decision Diagrams : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2.2 Computation Tree Logic : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2.3 The smv System : : : : : : : : : : : : : : : : : : : : : : : : ..."
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Cited by 9 (0 self)
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Contents 1 Introduction 3 2 Background 6 2.1 Ordered Binary Decision Diagrams : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2.2 Computation Tree Logic : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2.3 The smv System : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 2.4 Lineartime Temporal Logic : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 2.5 Fair Transition Systems : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 2.6 Enabled Transition Systems : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 9 3 The TLV system 13 3.1 The smv Input Language : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 14 3.2 The spl Input Language : : : : : : : : : : : : : : : : :
Using Timestamping and History Variables to Verify Sequential Consistency
 In Proceedings of the 13th International Conference on Computer Aided Verification (CAV 2001
, 2001
"... In this paper we propose a methodology for verifying the sequential consistency of caching algorithms. The scheme combines timestamping and an auxiliary history table to construct a serial execution `matching' any given execution of the algorithm. We believe that this approach is applicable ..."
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Cited by 8 (0 self)
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In this paper we propose a methodology for verifying the sequential consistency of caching algorithms. The scheme combines timestamping and an auxiliary history table to construct a serial execution `matching' any given execution of the algorithm. We believe that this approach is applicable to an interesting class of sequentially consistent algorithms in which the buffering of cache updates allows stale values to be read from cache. We illustrate this methodology by verifying the high level specifications of the lazy caching and ring algorithms.
A unified approach for combining different formalisms for hardware verification
 PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON FORMAL METHODS IN COMPUTERAIDED DESIGN, VOLUME 1166 OF LECTURE NOTES IN COMPUTER SCIENCE
, 1996
"... Model Checking as the predominant technique for automatically verifying circuits suffers from the wellknown state explosion problem. This hinders the verification of circuits which contain nontrivial data paths. Recently, it has been shown that for those circuits it may be useful to separate the c ..."
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Cited by 4 (1 self)
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Model Checking as the predominant technique for automatically verifying circuits suffers from the wellknown state explosion problem. This hinders the verification of circuits which contain nontrivial data paths. Recently, it has been shown that for those circuits it may be useful to separate the control and data part prior to verification. This paper is also based on this idea and presents an approach for combining various proof approaches like model checking and theorem proving in a unifying framework. In contrast to other approaches, special proof procedures are available to verify circuits with data sensitive controllers, where a bidirectional signal flow between controller and data path can be found. Generic circuits can be verified by induction or by model checking finite instantiations. By giving the system `proof hints', also the verification effort for model checking based proofs can be considerably reduced in many cases. The paper presents an introduction to the different proof strategies as well as an algorithm for their combination. The underlying C@S system also allows the efficiency evaluation of different approaches to verify the same circuits. This is shown in different case studies, demonstrating the tradeoff between interaction and verifiable circuit size.
Strategic principles in the design of Isabelle
 In CADE15 Workshop on Strategies in Automated Deduction
, 1998
"... Abstract. Interactive proof assistants can support proof strategies, if the right primitives have been included. These include higherorder syntax, logical variables and a choice of search primitives. Such asystem allows experimentation with di erent automatic proof methods, even for constructive lo ..."
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Cited by 3 (0 self)
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Abstract. Interactive proof assistants can support proof strategies, if the right primitives have been included. These include higherorder syntax, logical variables and a choice of search primitives. Such asystem allows experimentation with di erent automatic proof methods, even for constructive logics, new variablebinding operators, etc. The builtin uni cation and search make proof procedures easy to implement, typically using tableau methods. Against subgoals that arise in practice, even straightforward heuristics turn out to be powerful. 1
OPTIMIZING SLICING OF FORMAL SPECIFICATIONS BY DEDUCTIVE VERIFICATION
 NORDIC JOURNAL OF COMPUTING
, 2006
"... Slicing is a technique for extracting parts of programs or specifications with respect to certain criteria of interest. The extraction is carried out in such a way that properties as described by the slicing criterion are preserved, i.e., they hold in the complete program if and only if they hold in ..."
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Cited by 2 (0 self)
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Slicing is a technique for extracting parts of programs or specifications with respect to certain criteria of interest. The extraction is carried out in such a way that properties as described by the slicing criterion are preserved, i.e., they hold in the complete program if and only if they hold in the sliced program. During verification, slicing is often employed to reduce the state space of specifications to a size tractable by a model checker. The computation of specification slices relies on the construction of dependence graphs, reflecting (at least) control and data dependencies in specifications. The more dependencies the graph has, the less removal of parts is possible. In this paper we present a technique for optimizing the construction of the dependence graph by using deductive verification techniques. More precisely, we propose a technique for showing that certain control dependencies in the graph can be eliminated. The technique employs small deductive proofs of the enabledness of certain transitions. Thereby we obtain dependence graphs with less control dependencies and as a consequence smaller specification slices which are an easier target for model checking.