Results 11 - 20
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212
Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
- In Proc. DATE
, 2004
"... In this paper, we present a novel Energy-Aware Scheduling (EAS) algorithm which statically schedules both communication transactions and computation tasks onto heterogeneous Network-on-Chip (NoC) architectures under realtime constraints. Our algorithm automatically assigns tasks onto different proce ..."
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Cited by 55 (4 self)
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In this paper, we present a novel Energy-Aware Scheduling (EAS) algorithm which statically schedules both communication transactions and computation tasks onto heterogeneous Network-on-Chip (NoC) architectures under realtime constraints. Our algorithm automatically assigns tasks onto different processing elements and then schedules their execution. At the same time, the algorithm also takes into consideration the exact communication delay by scheduling communication transactions in parallel. As the main contribution, we first formulate the problem of concurrent communication and task scheduling for heterogeneous NoC architectures and then propose an efficient heuristic to solve it. Experimental results show that significant energy savings can be achieved by using our energy-aware scheduler while meeting the specified performance constraints. For instance, for a complex multimedia application, 44 % energy savings have been observed, on average, compared to the schedules generated by a standard earliest-deadline-first scheduler. 1
A methodology for mapping multiple usecases onto networks on chips
- DATE
, 2006
"... A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for fu-ture Systems on Chips (SoCs). As technology advances, the number of applications or use-cases integrated on a single chip increases rapid ..."
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Cited by 46 (5 self)
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A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for fu-ture Systems on Chips (SoCs). As technology advances, the number of applications or use-cases integrated on a single chip increases rapidly. The different use-cases of the SoC have different communication requirements (such as differ-ent bandwidth, latency constraints) and trafc patterns. The underlying NoC architecture has to satisfy the constraints of all the use-cases. In this work, we present a methodology to map multiple use-cases onto the NoC architecture, satis-fying the constraints of each use-case. We present dynamic re-conguration mechanisms that match the NoC congura-tion to the communication characteristics of each use-case, also accounting for use-cases that can run in parallel. The methodology is applied to several real and synthetic SoC benchmarks, which result in a large reduction in NoC area (an average of 80%) and power consumption (an average of 54%) compared to traditional design approaches.
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
- In Proc. Int’l Conference on VLSI Design
, 2004
"... We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for de ..."
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Cited by 41 (9 self)
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We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested and used. The concept includes support for best effort traffic packet delivery as well as for guaranteed bandwidth traffic using virtual circuits. Furthermore an application to NoC adapter is defined as part of the Resource to Network Interface, used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented and simulated and the results justifies the suggested layered approach.
An Application-Specific Design Methodology for On-Chip Crossbar Generation
- IEEE Trans. on CAD
, 2007
"... As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to in-crease, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent trend that many of the stan-dard bus produ ..."
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Cited by 41 (5 self)
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As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to in-crease, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent trend that many of the stan-dard bus products such as STbus, have now introduced the capability of designing a crossbar with multiple buses oper-ating in parallel. The crossbar configuration should be de-signed to closely match the application traffic characteris-tics and performance requirements. In this work we address this issue of application-specific design of optimal crossbar (using STbus crossbar architecture), satisfying the perfor-mance requirements of the application and optimal binding of cores onto the crossbar resources. We present a simula-tion based design approach that is based on analysis of ac-tual traffic trace of the application, considering local varia-tions in traffic rates, temporal overlap among traffic streams and criticality of traffic streams. Our methodology is ap-plied to several MPSoC designs and the resulting crossbar platforms are validated for performance by cycle-accurate SystemC simulation of the designs. The experimental case studies show large reduction in packet latencies (up to 7×) and large crossbar component savings (up to 3.5×) com-pared to traditional design approaches.
Application-specific Buffer Space Allocation for Networks-on-Chip Router Design
- in Proc. of the IEEE/ACM Intl. Conf. on Computer-aided Design
, 2004
"... In this paper, we present a novel system-level buffer planning algorithm that can be used to customize the router design in Networkson-Chip (NoCs). More precisely, given the traffic characteristics of the target application and the buffering space budget, our algorithm automatically assigns the buff ..."
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Cited by 41 (1 self)
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In this paper, we present a novel system-level buffer planning algorithm that can be used to customize the router design in Networkson-Chip (NoCs). More precisely, given the traffic characteristics of the target application and the buffering space budget, our algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip, to match the communication pattern, such that the overall performance is maximized. This is in deep contrast with the uniform assignment of buffering resources (currently used in NoC design) which can significantly degrade the overall system performance. For instance, for a complex audio/video application, about 85 % savings in buffering resources can be achieved by smart buffer allocation using our algorithm without any reduction in performance. 1.
Load distribution with the proximity congestion awareness in a network on chip
- In Proceedings of the Design Automation and Test Europe (DATE
, 2003
"... In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch. In case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the ma ..."
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Cited by 40 (13 self)
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In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch. In case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a Proximity Congestion Awareness, PCA, technique, where switches use load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20. 1
System-level buffer allocation for application-specific networks-on-chip router design
- IEEE TRANS. ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2006
"... In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic characteristics of the target application and the total budget of the available buffering space, the proposed algor ..."
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Cited by 37 (2 self)
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In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic characteristics of the target application and the total budget of the available buffering space, the proposed algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip, such that the overall performance is maximized. This is in deep contrast with the uniform assignment of buffering resources (currently used in NoC design), which can significantly degrade the overall system performance. Indeed, the experimental results show that while the proposed algorithm is very fast, significant performance improvements can be achieved compared to the uniform buffer allocation. For instance, for a complex audio/video application, about 80 % savings in buffering resources, can be achieved by smart buffer allocation using the proposed algorithm.
Mapping and Configuration Methods for Multi-use-case Networkson-Chip
- Proc. ASPDAC
, 2006
"... To provide a scalable communication infrastructure for Sys-tems on Chips (SoCs), Networks on Chips (NoCs), a communi-cation centric design paradigm is needed. To be cost effective, SoCs are often programmable and integrate several different applications or use-cases on to the same chip. For the SoC ..."
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Cited by 34 (4 self)
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To provide a scalable communication infrastructure for Sys-tems on Chips (SoCs), Networks on Chips (NoCs), a communi-cation centric design paradigm is needed. To be cost effective, SoCs are often programmable and integrate several different applications or use-cases on to the same chip. For the SoC platform to support the different use-cases, the NoC architec-ture should satisfy the performance constraints of each indi-vidual use-case. In this work we motivate the need to consider multiple use-cases during the NoC design process. We present a method to efficiently map the applications on to the NoC ar-chitecture, satisfying the design constraints of each individual use-case. We also present novel ways to dynamically recon-figure the network across the different use-cases and explore the possibility of integrating Dynamic Voltage and Frequency Scaling (DVS/DFS) techniques with the use-case centric NoC design methodology. We validate the performance of the de-sign methodology on several SoC applications. The dynamic reconfiguration of the NoC integrated with DVS/DFS schemes results in large power savings for the resulting NoC systems.
Xpipes Lite: A synthesis oriented design library for networks on chips
- In DATE
, 2005
"... The limited scalability of current bus topologies for Systems on Chips (SoCs) dictates the adoption of Networks on Chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While h ..."
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Cited by 32 (7 self)
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The limited scalability of current bus topologies for Systems on Chips (SoCs) dictates the adoption of Networks on Chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While highly parametric, fully synthesizeable (soft) NoC building blocks appear as a good match for heterogeneous MPSoC architectures, the impact of instantiation-time flexibility on performance, power and silicon cost has not been quantified yet. This work details ×pipes Lite, a design flow for automatic generation of heterogeneous NoCs. ×pipes Lite is based on highly customizable, high frequency and low latency NoC modules, that are fully synthesizeable. Synthesis results provide with modules that are directly comparable, if not better, than the current published state-of-theart NoCs in terms of area, power, latency and target frequency of operation measurements. 1.
Cost-Performance Trade-offs in Networks on Chip: A Simulation-Based Approach
- In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE
, 2004
"... A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency and throughput) . In this paper we present a simulation-based approach to address this problem. We use XML to instantiate n ..."
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Cited by 27 (9 self)
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A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency and throughput) . In this paper we present a simulation-based approach to address this problem. We use XML to instantiate network components (routers, network interfaces) and their composition. NoCs are evaluated in terms of cost and performance by sweeping over different parameters (e.g. network topology, network interface queue depth). We then show, how we can obtain trade-off plots by using the results obtained with our simulation environment. Finally, by means of two examples we illustrate how trade-off plots can help the NoC designers in selecting the right network based on a set of different constraints.
