Results 1  10
of
11
A Methodology for Hardware Verification Based on Logic Simulation
 Journal of the ACM
, 1991
"... A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulfilling the system specification will produce a particular response to a sequence of simulation commands. This style of verification has advantages over other proof methods in being readily a ..."
Abstract

Cited by 38 (4 self)
 Add to MetaCart
(Show Context)
A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulfilling the system specification will produce a particular response to a sequence of simulation commands. This style of verification has advantages over other proof methods in being readily automated and requiring less attention on the part of the user to the lowlevel details of the design. It has advantages over other approaches to simulation in providing more reliable results, often at a comparable cost.
Parametric Circuit Representation Using Inductive Boolean Functions
 In Computer Aided Verification, CAV '93, LNCS 697
, 1993
"... . We have developed a methodology based on symbolic manipulation of inductive Boolean functions (IBFs) for formal verification of inductivelydefined hardware. This methodology combines the techniques of reasoning by induction and symbolic tautologychecking in an automated and potentially efficient ..."
Abstract

Cited by 17 (2 self)
 Add to MetaCart
(Show Context)
. We have developed a methodology based on symbolic manipulation of inductive Boolean functions (IBFs) for formal verification of inductivelydefined hardware. This methodology combines the techniques of reasoning by induction and symbolic tautologychecking in an automated and potentially efficient way. In this paper, we describe a component of this methodology that regards various mechanisms used to represent inductivelydefined circuits in the form of IBFs. The focus is on general parameterization issues, such as multiple parameter functions, multiple output functions, interaction of different parameters for supporting compositions etc. These mechanisms, which may be useful in other applications involving parametric circuit descriptions, are illustrated through practical circuit examples along with preliminary results. We also describe an application of our formal verification methodology, where a proof by induction is performed by automatic symbolic manipulation of parametric circuit...
Formal Verification of Memory Circuits by SwitchLevel Simulation
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 1991
"... A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Threevalued modeling, where the third state indicates a signal with unknown digital ..."
Abstract

Cited by 11 (5 self)
 Add to MetaCart
(Show Context)
A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Threevalued modeling, where the third state indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete verification. As an extreme case, an bit randomaccess memory (RAM) can be verified by simulating just log patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switchlevel simulator. By simulating many patterns in parallel, a massivelyparallel computer can verify a 4K RAM in under 6 minutes. 1.
Verifying a Static RAM Design by Logic Simulation
 FIFTH MIT CONFERENCE ON ADVANCED RESEARCH IN VLSI
, 1988
"... ..."
Mechanically Verifying Safety and Liveness Properties of Delay Insensitive Circuits
 the BoyerMoore Prover. 1991 International Workshop on Formal Methods in VLSI Design
, 1994
"... This paper describes, by means of an example, how one may mechanically verify delay insensitive circuits on an automated theorem prover. It presents the verification of both the safety and liveness properties of an nnode delay insensitive FIFO circuit[20]. The proof system used is a mechanized impl ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
(Show Context)
This paper describes, by means of an example, how one may mechanically verify delay insensitive circuits on an automated theorem prover. It presents the verification of both the safety and liveness properties of an nnode delay insensitive FIFO circuit[20]. The proof system used is a mechanized implementation of Unity[7] on the BoyerMoore prover[4], described in [12]. This paper describes the circuit formally in the BoyerMoore logic and presents the mechanically verified correctness theorems. The formal description also captures the protocol that the circuit expects its environment to obey and specifies a class of suitable initial states. This paper demonstrates how a general purpose automated proof system for concurrent programs may be used to mechanically verify both the safety and liveness properties of arbitrary sized delay insensitive circuits. Keywords: Automated theorem proving, hardware verification, delay insensitive circuits. Author's Address: Naval Research Laboratory, C...
The Hardware Description Language Zeus
 IEEE Design and Test of Computers
, 1992
"... ..."
(Show Context)
The Retiming Lemma: A Simple Proof and Applications
 Integration: The VLSI Journal
, 1996
"... We present a new proof of the Retiming Lemma, which was first formulated and proved by Leiserson and Saxe [LS81]. Our proof relies on spacetime transformations, and shows how retiming can be interpreted in the domain of spacetime transformations. ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
(Show Context)
We present a new proof of the Retiming Lemma, which was first formulated and proved by Leiserson and Saxe [LS81]. Our proof relies on spacetime transformations, and shows how retiming can be interpreted in the domain of spacetime transformations.
algebra for digital design derivation 1 Research Prospectus Algebra for Digital Design Derivation
, 1989
"... This research investigates aspects of digital design in a functional algebra. The engineering paradigm is to obtain correct implementations through a sequence of algebraic transformations on a specification. This is synthesis in a formal framework; the term derivation is used to emphasize that sourc ..."
Abstract
 Add to MetaCart
This research investigates aspects of digital design in a functional algebra. The engineering paradigm is to obtain correct implementations through a sequence of algebraic transformations on a specification. This is synthesis in a formal framework; the term derivation is used to emphasize that source and target descriptions