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Lower Bounds and Exact Algorithms for the Graph Partitioning Problem using Multicommodity Flows
, 2001
"... In this paper new and generalized lower bounds for the graph partitioning problem are presented. These bounds base on the well known lower bound of embedding a clique into the given graph with minimal congestion which is equivalent to a multicommodity flow problem where each vertex sends a commodi ..."
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In this paper new and generalized lower bounds for the graph partitioning problem are presented. These bounds base on the well known lower bound of embedding a clique into the given graph with minimal congestion which is equivalent to a multicommodity flow problem where each vertex sends a commodity of size one to every other vertex. Our new bounds use arbitrary multicommodity flow instances for the bound calculation, the critical point for the lower bound is the guaranteed cut flow of the instances. Furthermore, a branch&bound procedure basing on these bounds is presented. Finally, upper bounds of the lower bounds are shown which demonstrate the superiority of the presented generalizations; and the new bounds are applied to the Butterfly and Benes network. 1
An assessment of highlevel partitioning techniques for implementing discrete signal transforms on distributed hardware architectures
 in Circuits and Systems, 2005. 48th Midwest Symposium on, 2005
"... Abstract — Partitioning is an essential step in the implementation of algorithms to distributed hardware architectures (DHAs) such as multiFPGA boards. While numerous approaches working at the structural level have been reported, techniques targeted at higher levels are less common. Moreover, when ..."
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Abstract — Partitioning is an essential step in the implementation of algorithms to distributed hardware architectures (DHAs) such as multiFPGA boards. While numerous approaches working at the structural level have been reported, techniques targeted at higher levels are less common. Moreover, when dealing with discrete signal transforms (DSTs), formulationlevel partitioners for DHAs have been largely neglected. In this paper, we introduce a first approach towards a functionallyaware methodology that could provide improved results for the highlevel partitioning of DSTs to DHAs. Our methodology has been devised through the study of DST partitioning techniques for DHAsimilar systems, as well as general DST formulation techniques. An assessment performed on discrete Fourier transforms has achieved as much as 35 % in latency reduction when compared to other general, highlevel partitioning schemes. I.
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
"... We solve an open question posed by Akers and Krishnamurthy in 1986 [1, 3] concerning VLSI layout of star graphs. We show that the area of the optimal layout of an Nnode star graph, hierarchical cubic network (HCN), or hierarchical foldedhypercube network (HFN) is N 2 =16 \Sigma o(N 2 ) under t ..."
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We solve an open question posed by Akers and Krishnamurthy in 1986 [1, 3] concerning VLSI layout of star graphs. We show that the area of the optimal layout of an Nnode star graph, hierarchical cubic network (HCN), or hierarchical foldedhypercube network (HFN) is N 2 =16 \Sigma o(N 2 ) under the Thompson model, or under the extended grid model where a node occupies a rectangle of sides that may range from n \Gamma 1 to o( p N) for the nstar, log 2 N + 1 to o( p N) for the HCN, and log 2 N + 2 to o( p N) for the HFN. An ndimensional star graph thus requires less area than any possible layout of a similarsize hypercube, but more than that of the much smaller ncube. We also derive multilayer layout for star graphs that has area N 2 8bL 2 =2c \Sigma o( N 2 L 2 ), where a node occupies a rectangle of sides ranging from d n\Gamma1 4 e to o( p N=L) and the number L of wiring layers satisfi es 2 L = o( p N=n). Finally we show that the bisection width of an Nnode star graph is N=4 \Sigma o(N) and the bisection width of an HCN or HFN is exactly N=4.
Vertex Bisection is hard, too
, 2009
"... We settle an open problem mentioned in Diaz, Petit, and Serna: A survey of graph layout problems (ACM Computing Surveys 34:313–356, 2002). Of eight objectives considered in that survey, only the complexity status of minimum vertex bisection is listed as unknown. We show that both minimum and maximum ..."
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Cited by 1 (0 self)
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We settle an open problem mentioned in Diaz, Petit, and Serna: A survey of graph layout problems (ACM Computing Surveys 34:313–356, 2002). Of eight objectives considered in that survey, only the complexity status of minimum vertex bisection is listed as unknown. We show that both minimum and maximum vertex bisection are N Phard, but polynomially solvable on special graph classes such as hypercubes and trees.
Improved Bounds on the Crossing Number of Butterfly Network
, 2013
"... We draw the r dimensional butterfly network with 1 4 4r +O(r2 r) crossings which improves the previous estimate given by Cimikowski (1996). We also give a lower bound which matches the upper bound obtained in this paper. ..."
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We draw the r dimensional butterfly network with 1 4 4r +O(r2 r) crossings which improves the previous estimate given by Cimikowski (1996). We also give a lower bound which matches the upper bound obtained in this paper.
1 DPillar: Scalable DualPort Server Interconnection for Data Center Networks
"... Abstract—Data centers are becoming increasingly important infrastructures for many essential applications such as data intensive computing and largescale network services. A typical future data center can consist of up to hundreds of thousands of servers. Yet, the conventional data center networks ..."
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Abstract—Data centers are becoming increasingly important infrastructures for many essential applications such as data intensive computing and largescale network services. A typical future data center can consist of up to hundreds of thousands of servers. Yet, the conventional data center networks are not able to keep up with the network bandwidth requirement for efficiently connecting that huge number of servers in a costefficient manner. It is hard to scale the hierarchical treebased interconnection network used in conventional data centers to support the massive amount of data communication in future data centers. In this paper, we present DPillar, a highly scalable data center interconnection architecture, which uses only lowend offtheshelf commodity PC servers and Ethernet switches. DPillar has minimal requirements for the equipment. The Ethernet switches can be lowcost plugandplay layer2 devices and the servers can be typical dualport commodity PCs. The salient feature of DPillar is that it expands to any number of servers without requiring to physically upgrading the existing servers. We present a simple yet efficient routing scheme that maintains short path length in server communications. We also propose faulttolerant and trafficaware routing schemes to ensure balanced load in the data center network. I.
VLSI Layout of Benes Networks
"... Abstract – The Benes network consists of backtoback butterflies. There exist a number of topological representations that are used to describe butterfly like architectures. We identify a new topological representation of Benes network. The significance of this representation is demonstrated by so ..."
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Abstract – The Benes network consists of backtoback butterflies. There exist a number of topological representations that are used to describe butterfly like architectures. We identify a new topological representation of Benes network. The significance of this representation is demonstrated by solving two problems, one related to VLSI layout and the other related to robotics. An important VLSI layout network problem is to produce the smallest possible grid area for realizing a given network. We propose an elegant VLSI layout of rdimensional Benes networks using this representation. The area of this layout is O(2 2r) whereas the lower bound for the area of the VLSI layout of Benes networks is O(2 2r). This lower bound is estimated by applying Thompson result.
Improved Bounds on the Crossing Number of Butterfly Network
, 2013
"... We draw the r dimensional butterfly network with 1 ..."
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