Behavioural synthesis currently seems to be an interesting design process to reduce the overall design cycle time substantially (from system level to physical level). Behavioural synthesis tools actually map algorithms to architectures and provide fast estimations of area and speed. This paper presents the synthesis of a complex application such the Viterbi algorithm, from behavioural synthesis up to logic synthesis. The differences between high level area and path delay estimations and real cost after logic and physical synthesis of a complex application are highlighted. Keywords Behavioural synthesis, digital ASIC design, interconnect cost estimations, Viterbi algorithm.