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Interconnect Cost Control during High-Level Synthesis
- in Proc. Int. Conf. Des. Circuits Integr. Syst
, 2000
"... Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease an ..."
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Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However, these tools do not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant with the technology decrease and the application complexity increase. A new methodology that enables the interconnection cost to be controlled all along the architectural synthesis process is presented in this paper. First experimental results are presented. Keywords: Architectural synthesis, digital ASIC design, interconnection cost, sub-micron technology, LMS filter.
SPÉCIALITÉ INFORMATIQUE Présentée par François DONNET Pour obtenir le titre de
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Architectural Synthesis with Interconnection Cost Control
, 1999
"... Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application comp ..."
Abstract
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Architectural synthesis tools map algorithms to architectures under various constraints and quickly provide estimations of area and performance. However, these tools do not take the interconnection cost into account whereas it becomes predominant with the technology decrease and the application complexity increase. A way to control costly interconnections during the architectural process is presented in this paper. Keywords: Architectural synthesis, digital ASIC design, sub-micron technologies, interconnection cost
Archiectural Synthesis of Digital Signal Processing Applications Dedicated to Submicron Technologies
, 2001
"... Architectural synthesis is an efficient design process that reduces the gap between algorithms and architectures by raising the abstraction level. However, this process currently does not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant using submicron te ..."
Abstract
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Architectural synthesis is an efficient design process that reduces the gap between algorithms and architectures by raising the abstraction level. However, this process currently does not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant using submicron technologies. In this paper, an interconnection cost analysis at the behavioural level is performed in order to provide rapid prototyping results and to direct the synthesis process with additional path constraints. Results are presented showing the interest of this approach. 1.
