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36
The ForSpec Temporal Logic: A New Temporal PropertySpecification Language
, 2001
"... In this paper we describe the ForSpec Temporal Logic (FTL), the new temporal propertyspecification logic of ForSpec, Intel's new formal specification language. The key features of FTL are as follows: it is a linear temporal logic, based on Pnueli's LTL, it is based on a rich set of log ..."
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Cited by 89 (22 self)
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In this paper we describe the ForSpec Temporal Logic (FTL), the new temporal propertyspecification logic of ForSpec, Intel's new formal specification language. The key features of FTL are as follows: it is a linear temporal logic, based on Pnueli's LTL, it is based on a rich set of logical and arithmetical operations on bit vectors to describe state properties, it enables the user to define temporal connectives over time windows, it enables the user to define regular events, which are regular sequences of Boolean events, and then relate such events via special connectives, it enables the user to express properties about the past, and it includes constructs that enable the user to model multiple clock and reset signals, which is useful in the verification of hardware design.
Executing higher order logic
 IN PROC. TYPES WORKING GROUP ANNUAL MEETING 2000, LNCS
, 2002
"... We report on the design of a prototyping component for the theorem prover Isabelle/HOL. Specifications consisting of datatypes, recursive functions and inductive definitions are compiled into a functional program. Functions and inductively defined relations can be mixed. Inductive definitions must b ..."
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Cited by 59 (18 self)
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We report on the design of a prototyping component for the theorem prover Isabelle/HOL. Specifications consisting of datatypes, recursive functions and inductive definitions are compiled into a functional program. Functions and inductively defined relations can be mixed. Inductive definitions must be such that they can be executed in Prolog style but requiring only matching rather than unification. This restriction is enforced by a mode analysis. Tail recursive partial functions can be defined and executed with the help of a while combinator.
An Industrially Effective Environment for Formal Hardware Verification
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
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The PROSPER Toolkit
, 2000
"... The Prosper (Proof and Specification Assisted Design Environments) project advocates the use of toolkits which allow existing verification tools to be adapted to a more flexible format so that they may be treated as components. A system incorporating such tools becomes another component that can be ..."
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Cited by 45 (2 self)
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The Prosper (Proof and Specification Assisted Design Environments) project advocates the use of toolkits which allow existing verification tools to be adapted to a more flexible format so that they may be treated as components. A system incorporating such tools becomes another component that can be embedded in an application. This paper describes the Prosper Toolkit which enables this. The nature of communication between components is specified in a languageindependent way. It is implemented in several common programming languages to allow a wide variety of tools to have access to the toolkit.
A Reflective Functional Language for Hardware Design and Theorem Proving
"... This paper introduces reFLect, a functional programming language with reflection features intended for applications in hardware design and verification. The reFLect language is strongly typed and similar to ML, but has quotation and antiquotation constructs. These may be used to construct and decomp ..."
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Cited by 32 (7 self)
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This paper introduces reFLect, a functional programming language with reflection features intended for applications in hardware design and verification. The reFLect language is strongly typed and similar to ML, but has quotation and antiquotation constructs. These may be used to construct and decompose expressions in the reFLect language itself. The paper motivates and presents the syntax and type system of this language, which brings together a new combination of patternmatching and reflection features targeted specifically at our application domain. It also gives an operational semantics based on a new use of contexts as expression constructors, and it presents a scheme for compiling reFLect programs into the λcalculus using the same context mechanism.
A methodology for largescale hardware verification
 Formal Methods in ComputerAided Design: 3rd International Conference, FMCAD, volume 1954 of LNCS
, 2000
"... Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities undertaken in largescale verification efforts and to structure the associated code and proofscript artifacts. The methodo ..."
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Cited by 16 (4 self)
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Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities undertaken in largescale verification efforts and to structure the associated code and proofscript artifacts. The methodology deploys a combination of model checking and lightweight theorem proving in higherorder logic, tightly integrated within a generalpurpose functional programming language that allows the framework to be easily customized and also serves as a specification language. We illustrate the methodology—which has has proved highly effective in largescale industrial trials—with the verification of an IEEEcompliant, extended precision floatingpoint adder. 1
A thread of HOL development
 Computer Journal
"... The HOL system is a mechanized proof assistant for higher order logic that has been under continuous development since the mid1980s, by an everchanging group of developers and external contributors. We give a brief overview of various implementations of the HOL logic before focusing on the evoluti ..."
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Cited by 12 (7 self)
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The HOL system is a mechanized proof assistant for higher order logic that has been under continuous development since the mid1980s, by an everchanging group of developers and external contributors. We give a brief overview of various implementations of the HOL logic before focusing on the evolution of certain important features available in a recent implementation. We also illustrate how the module system of Standard ML provided security and modularity in the construction of the HOL kernel, as well as serving in a separate capacity as a useful representation medium for persistent, hierarchical logical theories.
Floatingpoint verification
 International Journal Of ManMachine Studies
, 1995
"... Abstract: This paper overviews the application of formal verification techniques to hardware in general, and to floatingpoint hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible and verifia ..."
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Cited by 9 (0 self)
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Abstract: This paper overviews the application of formal verification techniques to hardware in general, and to floatingpoint hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible and verifiable way.
Hierarchical Verification Using an MDGHOL Hybrid Tool
"... We describe a hybrid formal hardware verification tool that links the HOL interactive proof system and the MDG automated hardware verification tool. It supports a hierarchical verification approach that mirrors the hierarchical structure of designs. We obtain advantages of both verification paradi ..."
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Cited by 8 (2 self)
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We describe a hybrid formal hardware verification tool that links the HOL interactive proof system and the MDG automated hardware verification tool. It supports a hierarchical verification approach that mirrors the hierarchical structure of designs. We obtain advantages of both verification paradigms. We illustrate its use by considering a component of a communications chip. Verification with the hybrid tool is significantly faster and more tractable than using either tool alone.
Formal Verification of Iterative Algorithms in Microprocessors
, 2000
"... Contemporary microprocessors implement many iterative algorithms. For example, the frontend of a microprocessor repeatedly fetches and decodes instructions while updating internal state such as the program counter; floatingpoint circuits perform divide and square root computations iteratively. Ite ..."
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Cited by 8 (0 self)
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Contemporary microprocessors implement many iterative algorithms. For example, the frontend of a microprocessor repeatedly fetches and decodes instructions while updating internal state such as the program counter; floatingpoint circuits perform divide and square root computations iteratively. Iterative algorithms often have complex implementations because of performance optimizations like result speculation, retiming and circuit redundancies. Verifying these iterative circuits against highlevel specifications requires two steps: reasoning about the algorithm itself and verifying the implementation against the algorithm. In this paper we discuss the verification of four iterative circuits from Intel microprocessor designs. These verifications were performed using Forte, a custombuilt verification system; we discuss the Forte features necessary for our approach. Finally, we discuss how we maintained these proofs in the face of evolving design implementations.