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Hybrid Static–Dynamic Analysis for Statically Bounded Region Serializability
, 2015
"... Data races are common. They are difficult to detect, avoid, or eliminate, and programmers sometimes introduce them intentionally. However, shared-memory programs with data races have unexpected, erroneous behaviors. Intentional and unintentional data races lead to atomicity and sequential consistenc ..."
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Cited by 5 (4 self)
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Data races are common. They are difficult to detect, avoid, or eliminate, and programmers sometimes introduce them intentionally. However, shared-memory programs with data races have unexpected, erroneous behaviors. Intentional and unintentional data races lead to atomicity and sequential consistency (SC) violations, and they make it more difficult to understand, test, and verify software. Existing approaches for providing stronger guarantees for racy executions add high run-time overhead and/or rely on custom hardware. This paper shows how to provide stronger semantics for racy programs while providing relatively good performance on commodity systems. A novel hybrid static–dynamic anal-ysis called EnfoRSer provides end-to-end support for a memory model called statically bounded region serializ-ability (SBRS) that is not only stronger than weak memory models but is strictly stronger than SC. EnfoRSer uses static compiler analysis to transform regions, and dynamic anal-ysis to detect and resolve conflicts at run time. By demon-strating commodity support for a reasonably strong memory model with reasonable overheads, we show its potential as an always-on execution model.
Idempotent Code Generation: Implementation, Analysis, and Evaluation
"... Leveraging idempotence for efficient recovery is of emerging interest in compiler design. In particular, identifying semantically idempotent code and then compiling such code to preserve the semantic idempotence property enables recovery with substantially lower overheads than competing software tec ..."
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Cited by 4 (1 self)
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Leveraging idempotence for efficient recovery is of emerging interest in compiler design. In particular, identifying semantically idempotent code and then compiling such code to preserve the semantic idempotence property enables recovery with substantially lower overheads than competing software techniques. However, the efficacy of this technique depends on application-, architecture-, and compiler-specific factors that are not well understood. In this paper, we develop algorithms for the code generation of idempotent code regions and evaluate these algorithms considering how they are impacted by these factors. Without optimizing for these factors, we find that typical performance overheads fall in the range of roughly 10-15%. However, manipulating application idempotent region size typically improves the run-time performance of compiled code by 2-10%, differences in the architecture instruction set affect performance by up to 15%, and knowing in the compiler whether control flow side-effects can or cannot occur can impact performance by up to 10%. Overall, we find that, with small idempotent region and careful architecture- and application-specific tuning, it is possible to bring compiler performance overheads consistently down into the single-digit percentage range. The absolute best performance occurs when constructing the largest possible idempotent regions; to this end, however, better compiler support is needed. In the interest of spurring development in this area, we open-source our LLVM compiler implementation and make it available as a research tool.
Speculative Memory Checkpointing
"... High-frequency memory checkpointing is an important tech-nique in several application domains, such as automatic error recovery (where frequent checkpoints allow the sys-tem to transparently mask failures) and application debug-ging (where frequent checkpoints enable fast and accurate time-traveling ..."
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High-frequency memory checkpointing is an important tech-nique in several application domains, such as automatic error recovery (where frequent checkpoints allow the sys-tem to transparently mask failures) and application debug-ging (where frequent checkpoints enable fast and accurate time-traveling support). Unfortunately, existing (typically incremental) checkpointing frameworks incur substantial per-formance overhead in high-frequency memory checkpointing applications, thus discouraging their adoption in practice. This paper presents Speculative Memory Checkpointing (SMC), a new low-overhead technique for high-frequency memory checkpointing. Our motivating analysis identifies key bottlenecks in existing frameworks and demonstrates that the performance of traditional incremental checkpoint-ing strategies in high-frequency checkpointing scenarios is not optimal. To fill the gap, SMC relies on working set estimation algorithms to eagerly checkpoint the memory pages that belong to the writable working set of the run-ning program and only lazily checkpoint the memory pages that do not. Our experimental results demonstrate that SMC is effective in reducing the performance overhead of prior solutions, is robust to variations in the workload, and incurs modest memory overhead compared to traditional incremental checkpointing.
AI: A Lightweight System for Tolerating Concurrency Bugs
"... Concurrency bugs are notoriously difficult to eradicate during software testing because of their non-deterministic nature. More-over, fixing concurrency bugs is time-consuming and error-prone. Thus, tolerating concurrency bugs during production runs is an at-tractive complementary approach to bug de ..."
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Concurrency bugs are notoriously difficult to eradicate during software testing because of their non-deterministic nature. More-over, fixing concurrency bugs is time-consuming and error-prone. Thus, tolerating concurrency bugs during production runs is an at-tractive complementary approach to bug detection and testing. Un-fortunately, existing bug-tolerating tools are usually either 1) con-strained in types of bugs they can handle or 2) requiring roll-back mechanism, which can hitherto not be fully achieved efficiently without hardware supports. This paper presents a novel program invariant, called Anticipat-ing Invariant (AI), which can help anticipate bugs before any irre-versible changes are made. Benefiting from this ability of anticipat-ing bugs beforehand, our software-only system is able to forestall the failures with a simple thread stalling technique, which does not rely on execution roll-back and hence has good performance Experiments with 35 real-world concurrency bugs demonstrate that AI is capable of detecting and tolerating most types of con-currency bugs, including both atomicity and order violations. Two new bugs have been detected and confirmed by the corresponding developers. Performance evaluation with 6 representative parallel programs shows that AI incurs negligible overhead (< 1%) for many nontrivial desktop and server applications.
