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17
Maxplus algebra
, 2006
"... Maxplus algebra has been discovered more or less independently by several schools, in relation with various mathematical fields. This chapter is limited to finite dimensional linear algebra. For more information, the reader may consult the books [CG79, Zim81, CKR84, BCOQ92, KM97, GM02]. The collect ..."
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Cited by 35 (5 self)
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Maxplus algebra has been discovered more or less independently by several schools, in relation with various mathematical fields. This chapter is limited to finite dimensional linear algebra. For more information, the reader may consult the books [CG79, Zim81, CKR84, BCOQ92, KM97, GM02]. The collections of articles [MS92, Gun98, LM05] give a good idea of current developments.
Retiming for Wire Pipelining in SystemOnChip
, 2003
"... At the integration scale of SystemOnChips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple ..."
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Cited by 23 (9 self)
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At the integration scale of SystemOnChips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multipleclock period wires. In this paper, we explore retiming to pipeline long interconnect wires in SOC designs. Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macroblocks, where the internal structures may not be changed and flipflops may not be able to be inserted on some wire segments. This problem is different from that on a gate level netlist and is formulated as a wire retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results showed the benefits and effectiveness of our approach.
Physical placement driven by sequential timing analysis
 Proc. ICCAD '04
, 2004
"... Traditional timingdriven placement considers only combinarional delays and does not take into account rhe potenrial of subsequent sequenrial optimization steps. As a resulr, the porential of rebalancing path delays rhrough posrplacement applications of clock skew scheduling and inplace retimin ..."
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Cited by 13 (2 self)
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Traditional timingdriven placement considers only combinarional delays and does not take into account rhe potenrial of subsequent sequenrial optimization steps. As a resulr, the porential of rebalancing path delays rhrough posrplacement applications of clock skew scheduling and inplace retiming cannot be fully realized. In this paper we describe a new placement algorirhm rhat is based on a tighr integration of sequenrial timing analysis in the inner loop of an analytic solver: Instead of minimizing the maximum path delay, our approach minimizes the maximum mean delay on any circuit loop, rhus enabling the full optimization potenrial of clock skew scheduling and inplace reriming. We presenr iwo versions of the new algorirhm: one appm,rimares sequenrial criticality and weights wires accordingly [I], the orher extends rhis with rhe inclusion of erplicir wirelength constraints for loops rhat limit the final clock period. Our algorithms are implemented using a hybrid, GORDIANstyle sequence of analyticalplacement steps interleaved with cell partitioning [21. Our experiments on a set of large industrial designs demonstrare that the presented placement algorithm can minimize the contribution of interconnection delays to the clock period on average by 23.5 % compared io a solution based on combinational delays. 1
Timing Analysis of Embedded RealTime Systems
 PhD thesis, UIUC technical reports UIUCDCSR992079 and UILUENG991702., Univ. of Illinois at UrbanaChampaign
, 1999
"... We address the problem of timing constraint derivation and validation for reactive and realtime embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the sys ..."
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Cited by 7 (2 self)
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We address the problem of timing constraint derivation and validation for reactive and realtime embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: (1) a generalized task graph model and a comprehensive classification of timing constraints, (2) algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, (3) new and improved algorithms for finding the performance of cyclic embedded systems and a comprehensive comparison of the existing algorithms, (4) a general formulation of the problem of debugging timing violations in cyclic embedded systems and it...
Optimal embedding into star metrics
 In Proc. 11th Workshop on Algorithms and Data Structures
, 2009
"... Abstract. We present an O(n 3 log 2 n)time algorithm for the following problem: given a finite metric space X, create a startopology network with the points of X as its leaves, such that the distances in the star are at least as large as in X, with minimum dilation. As part of our algorithm, we so ..."
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Cited by 2 (1 self)
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Abstract. We present an O(n 3 log 2 n)time algorithm for the following problem: given a finite metric space X, create a startopology network with the points of X as its leaves, such that the distances in the star are at least as large as in X, with minimum dilation. As part of our algorithm, we solve in the same time bound the parametric negative cycle detection problem: given a directed graph with edge weights that are increasing linear functions of a parameter λ, find the smallest value of λ such that the graph contains no negativeweight cycles. 1
Faster Algorithms for Quantitative Verification in Constant Treewidth Graphs
"... Abstract. We consider the core algorithmic problems related to verification of systems with respect to three classical quantitative properties, namely, the meanpayoff property, the ratio property, and the minimum initial credit for energy property. The algorithmic problem given a graph and a quant ..."
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Cited by 1 (1 self)
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Abstract. We consider the core algorithmic problems related to verification of systems with respect to three classical quantitative properties, namely, the meanpayoff property, the ratio property, and the minimum initial credit for energy property. The algorithmic problem given a graph and a quantitative property asks to compute the optimal value (the infimum value over all traces) from every node of the graph. We consider graphs with constant treewidth, and it is wellknown that the controlflow graphs of most programs have constant treewidth. Let n denote the number of nodes of a graph, m the number of edges (for constant treewidth graphs m = O(n)) and W the largest absolute value of the weights. Our main theoretical results are as follows. First, for constant treewidth graphs we present an algorithm that approximates the meanpayoff value within a multiplicative factor of in time O(n · log(n/)) and linear space, as compared to the classical algorithms that require quadratic time. Second, for the ratio property we present an algorithm that for constant treewidth graphs works in time O(n · log(a · b)) = O(n · log(n ·W)), when the output is a b, as compared to the previously best known algorithm with running time O(n2 · log(n ·W)). Third, for the minimum initial credit problem we show that (i) for general graphs the problem can be solved in O(n2 ·m) time and the associated decision problem can be solved inO(n ·m) time, improving the previous known O(n3 · m · log(n · W)) and O(n2 · m) bounds, respectively; and (ii) for constant treewidth graphs we present an algorithm that requires O(n · logn) time, improving the previous known O(n4 · log(n ·W)) bound. We have implemented some of our algorithms and show that they present a significant speedup on standard benchmarks. 1
Policy Iteration Algorithm For Shortest Path Problems
"... . The shortest paths tree problem consists in finding a spanning tree rooted at a given node, in a directed weighted graph, such that for each node i , the path of the tree which goes from i to the root has minimal weight. We propose an algorithm which is a deterministic version of Howard's pol ..."
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Cited by 1 (0 self)
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. The shortest paths tree problem consists in finding a spanning tree rooted at a given node, in a directed weighted graph, such that for each node i , the path of the tree which goes from i to the root has minimal weight. We propose an algorithm which is a deterministic version of Howard's policy iteration scheme. We show that policy iteration is faster than the Bellman (or value iteration) algorithm. In particular, the worst case execution time of policy iteration is O(nm), where n is the number of nodes, and m is the number of arcs. Policy iteration finds rapidly a circuit of negative weight when there is one. R esum e. Le probleme de l'arbre des plus courts chemins consiste a trouver un arbre couvrant de racine donnee dans un graphe oriente value, tel que pour tout sommet i , le chemin de l'arbre qui va de i a la racine a un poids minimum. Nous proposons un algorithme qui est une version deterministe de l'iteration sur les politiques d'Howard. Nous montrons que l'iteration sur les...
HighLevel Synthesis of DSP Applications using Adaptive Negative Cycle Detection
, 2002
"... Detection of negative cycles in a weighted directed graph is a problem that plays an important role in the highlevel synthesis (HLS) of DSP applications. In this paper, this problem is examined in the context of the "dynamic graph" structures that arise in the process of HLS. The concept ..."
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Detection of negative cycles in a weighted directed graph is a problem that plays an important role in the highlevel synthesis (HLS) of DSP applications. In this paper, this problem is examined in the context of the "dynamic graph" structures that arise in the process of HLS. The concept of adaptive negative cycle detection is introduced, in which a graph changes over time and negative cycle detection needs to be done periodically, but not necessarily after every individual change. Such scenarios arise, for example, during iterative design space exploration for hardware and software synthesis. We present an algorithm for this problem, based on a novel extension of the well known BellmanFord algorithm that allows us to adapt our existing cycle information to the modified graph, and show by experimental results that our algorithm significantly outperforms previous approaches for dynamic graphs, which do not take advantage of multiple simultaneous changes to the graph and require excessive computation. The adaptive technique introduced here is used to solve two important problems in the HLS process: performance analysis and system synthesis. The adaptive technique leads to a very fast implementation of Lawler's algorithm for the computation of the maximumcycle mean (MCM) of a graph, especially for a certain form of sparse graph. Such sparseness often occurs in practical circuits and systems, as demonstrated for example by the ISCAS 89/93 benchmarks. The application of the adaptive technique to designspace exploration (synthesis) is also demonstrated by developing automated search techniques for scheduling iterative dataflow graphs.
Physical Placement Driven by Sequential Timing Analysis
"... Traditional timingdriven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the potential of rebalancing path delays through postplacement applications of clock skew scheduling and inplace retiming ..."
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Traditional timingdriven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the potential of rebalancing path delays through postplacement applications of clock skew scheduling and inplace retiming cannot be fully realized. In this paper we describe a new placement algorithm that is based on a tight integration of sequential timing analysis in the inner loop of an analytic solver. Instead of minimizing the maximum path delay, our approach minimizes the maximum mean delay on any circuit loop, thus enabling the full optimization potential of clock skew scheduling and inplace retiming. We present two versions of the new algorithm: one approximates sequential criticality and weights wires accordingly [1], the other extends this with the inclusion of explicit wirelength constraints for loops that limit the final clock period. Our algorithms are implemented using a hybrid, GORDIANstyle sequence of analytical placement steps interleaved with cell partitioning [2]. Our experiments on a set of large industrial designs demonstrate that the presented placement algorithm can minimize the contribution of interconnection delays to the clock period on average by 23.5 % compared to a solution based on combinational delays. 1