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55
Test Set Compaction Algorithms for Combinational Circuits
, 2000
"... This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic co ..."
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Cited by 156 (5 self)
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This paper presents a new algorithm, Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits. Keywords test set compaction, minimum test set size estimation, test generation, combinational circuits, stuck-at fault model. 2 Footnotes I. Hamzaoglu was with Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL 61801. He is now with Motorola Labs, 1301 E. Algonquin Road, Schaumburg, IL 60196. J. H. Patel is with Center for Reliable & High-Performance Computing, Univers...
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors
- Journal of Symbolic Computation
, 2001
"... We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its per ..."
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Cited by 101 (17 self)
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We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.
Fault diagnosis and logic debugging using Boolean satisfiability
- IEEE TRANS. ON CAD
, 2005
"... Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scaleintegration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. ..."
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Cited by 73 (32 self)
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Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital very-large-scaleintegration design problems. Although useful in many stages of the design cycle, fault diagnosis and logic debugging have not been addressed within a satisfiability-based framework. This work proposes a novel Boolean satisfiability-based method for multiple-fault diagnosis and multiple-design-error diagnosis in combinational and sequential circuits. A number of heuristics are presented that keep the method memory and run-time efficient. An extensive suite of experiments on large circuits corrupted with different types of faults and errors confirm its robustness and practicality. They also suggest that satisfiability captures significant characteristics of the problem of diagnosis and encourage novel research in satisfiability-based diagnosis as a complementary process to design verification.
SPIRIT: A Highly Robust Combinational Test Generation Algorithm
- 19 th IEEE Proc. on VTS, 2001
, 2001
"... In this paper, we present a robust test generation algorithm for combinational circuits based on the Boolean satisfiability method called SPIRIT. We elaborate some well-known techniques as well as present new techniques that improve the performance and robustness of test generation algorithms. As a ..."
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Cited by 17 (2 self)
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In this paper, we present a robust test generation algorithm for combinational circuits based on the Boolean satisfiability method called SPIRIT. We elaborate some well-known techniques as well as present new techniques that improve the performance and robustness of test generation algorithms. As a result, SPIRIT achieves 100 % fault efficiency for a full scan version of the ITC'99 benchmark circuits in a reasonable amount of time. 1.
Column-Matching BIST Exploiting Test Don't-Cares
- PROC. 8TH IEEE EUROPEAN TEST WORKSHOP (ETW'03), MAASTRICHT (THE NETHERLANDS)
, 2003
"... We propose a new test-per-clock BIST method for combinational or full-scan circuits. Our aim is to design a combinational block transforming the LFSR code words into deterministic test patterns pre-computed by some ATPG tool. The proposed algorithm is an enhancement of a column matching method, in w ..."
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Cited by 15 (8 self)
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We propose a new test-per-clock BIST method for combinational or full-scan circuits. Our aim is to design a combinational block transforming the LFSR code words into deterministic test patterns pre-computed by some ATPG tool. The proposed algorithm is an enhancement of a column matching method, in which the maximum of the output variables of the decoder is tried to be implemented as mere wires, thus without any logic. The enhancement consists in extending the use of the method for a test set containing don't cares. These don't cares allow us to reach a higher number of column matches, which significantly reduces the BIST logic.
Design Rewiring Using ATPG
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2002
"... Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power, or delay. Recently, automated test pattern generation (ATPG)-based design rewiring techniques for technol ..."
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Cited by 14 (10 self)
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Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints such as area, power, or delay. Recently, automated test pattern generation (ATPG)-based design rewiring techniques for technology-dependent logic optimization have gained increasing popularity. In this paper, the authors propose a new operational framework to design rewiring that uses ATPG and diagnosis algorithms. They also examine its complexity requirements and discuss different implementation tradeoffs. To perform this study, the authors reduce the problem of design rewiring to the process of injecting a redundant set of multiple pattern faults. This formulation arrives at a new set of results with theoretical and practical applications. Experiments demonstrate the competitiveness of the approach and motivate future work in the area.
Multiple scan chains for power minimization during test application in sequential circuits
- IEEE Trans. on Computers
, 2002
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Constrained ATPG for Broadside Transition Testing
- In Int’l Symp. on Defect and Fault Tolerance in VLSI Systems
, 2003
"... In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally untestable transition fault , a set of illegal (unreachable) states that enable detection of is first computed. This ..."
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Cited by 12 (2 self)
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In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally untestable transition fault , a set of illegal (unreachable) states that enable detection of is first computed. This set of undesirable illegal states is efficiently represented as a Boolean formula. Our constrained ATPG then incorporates this constraint formula to generate Broadside vectors that avoid those undesirable states. In doing so, our method efficiently generates a test set for functionally testable transition faults and minimizes detection of functionally untestable transition faults. Because we want to avoid launching and propagating transitions in the circuit that are not possible in the functional mode, a direct benefit of our method is the reduction of yield loss due to overtesting of these functionally untestable transitions. 1
Implication and Evaluation Techniques for Proving Fault Equivalence
- in Proc. 17th IEEE VLSI Test Symp
, 1999
"... Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluatio ..."
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Cited by 11 (2 self)
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Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence. 1 Introduction Recent literature on diagnosis [1, 2] shows that a significant fraction of fault pairs that remain indistinguished after applying a complete fault detection test set are, in fact, equivalent. Thus, diagnostic test pattern generators spend considerable effort on attempting to distinguish indistinguishable fault pairs. The problem of identifying fault equivalence of a fault pair in diagno...
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
, 2000
"... This paper presents a new technique, called Ccompatibility, for reducing the test application time of the counter-based exhaustive Built-in-Self-Test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern g ..."
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Cited by 11 (0 self)
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This paper presents a new technique, called Ccompatibility, for reducing the test application time of the counter-based exhaustive Built-in-Self-Test (BIST) test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the test pattern generators. We have incorporated the synthesis algorithm for synthesizing BIST test pattern generators using the C-compatibility technique into ATOM, an advanced ATPG system for combinational circuits. The experimental results showed that the test pattern generators synthesized using this technique for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits achieve 100% stuck-at fault coverage in much smaller test application time than the previously published counterbased exhaustive BIST test pattern generators.
