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Automated Bus Generation for Multiprocessor SoC Design
, 2003
"... The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis tool (BusSyn) uses this methodology to genera ..."
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Cited by 21 (0 self)
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The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor System-on-a-Chip (SoC). Our bus synthesis tool (BusSyn) uses this methodology to generate five different bus systems as examples: Bi-FIFO Bus Architecture (BFBA), Global Bus Architecture Version I (GBAVI), Global Bus Architecture Version III (GBAVIII), Hybrid bus architecture (Hybrid) and Split Bus Architecture (SplitBA). We verify and evaluate the performance of each bus system in the context of two applications: an Orthogonal Frequency Division Multiplexing (OFDM) wireless transmitter and an MPEG2 decoder. This methodology gives the designer a great benefit in fast design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types and software programming style. In this paper, we show that BusSyn can generate buses that achieve superior performance when compared to a simple General Global Bus Architecture (GGBA) (e.g., 16.44% performance improvement in the case of OFDM transmitter) or when compared to the CoreConnect Bus Architecture (CCBA) (e.g., 15.54% peformance improvement in the case of MPEG2 decoder). In addition, the bus architecture generated by BusSyn is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.
Automatic Communication Refinement for System Level Design
, 2003
"... This paper presents a methodology and algorithms for automatic communication refinement. The communication refinement task in system-level synthesis transforms abstract data-transfer between components to its actual bus level implementation. The input model of the communication refinement is a set o ..."
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Cited by 19 (4 self)
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This paper presents a methodology and algorithms for automatic communication refinement. The communication refinement task in system-level synthesis transforms abstract data-transfer between components to its actual bus level implementation. The input model of the communication refinement is a set of concurrently executing components, communicating with each other through abstract communication channels. The refined model reflects the actual communication architecture. Choosing a good communication architecture in system level designs requires sufficient exploration through evaluation of various architectures. However, this would not be possible with manually refining the system model for each communication architecture. For one, manual refinement is tedious and error-prone. Secondly, it wastes substantial amount of precious designer time. We solve this problem with automatic model refinement. We also present a set of experimental results to demonstrate how the proposed approach works on a typical system level design
Hardware and Interface Synthesis of FPGA Blocks Using Parallelizing Code Transformations
"... Reconfigurable logic such as FPGAs is increasingly being used on system-on-chip (SoC) platforms to provide a flexible, programmable co-processor that augments the core processor. In this paper, we present a tightly coupled hardware synthesis and interface synthesis approach that forms part of our ha ..."
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Cited by 7 (1 self)
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Reconfigurable logic such as FPGAs is increasingly being used on system-on-chip (SoC) platforms to provide a flexible, programmable co-processor that augments the core processor. In this paper, we present a tightly coupled hardware synthesis and interface synthesis approach that forms part of our hardware-software co-design methodology for such FPGA-based platforms. For hardware synthesis, we use a parallelizing high-level synthesis approach that employs aggressive coarse-grain and fine-grain code parallelizing and code motion techniques to discover circuit optimization opportunities beyond what is possible with traditional high-level synthesis. We have implemented this approach in a framework called Spark that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL. Our interface synthesis approach is based on a novel memory mapping algorithm that uses scheduling information from the high-level synthesis tool to map data used by both the hardware and the software to shared memories on the reconfigurable fabric. We present experimental results for the synthesis of computationally intensive portions of multimedia applications that demonstrate that the code transformations in Spark lead to up to 50-70 % improvements in circuit delay with fairly constant circuit area. We also present a case study of the hardware-software co-design of a portion of multimedia application onto a FGPA platform using our methodology. KEY WORDS System synthesis, high-level synthesis, interface synthesis, parallelizing transformations, FPGA, platform design 1
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"... Abstract: Human-Robot interaction (HRI) has recently become one of the most important issues in the field of robotics. Understanding and predicting the intentions of human users is a major difficulty for robotic programs. In this paper we suggest an interaction method allows the robot to execute th ..."
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Abstract: Human-Robot interaction (HRI) has recently become one of the most important issues in the field of robotics. Understanding and predicting the intentions of human users is a major difficulty for robotic programs. In this paper we suggest an interaction method allows the robot to execute the human user's desires in an intelligent room-based domain, even when the user does not give a specific command for the action. To achieve this, we constructed a full system architecture of an intelligent room so that the following were present and sequentially interconnected: decision-making based on the Bayesian belief network, responding to human commands, and generating queries to remove ambiguities. The robot obtained all the necessary information from analyzing the user's condition and the environmental state of the room. This information is then used to evaluate the probabilities of the results coming from the output nodes of the Bayesian belief network, which is composed of the nodes that includes several states, and the causal relationships between them. Our study shows that the suggested system and proposed method would improve a robot's ability to understand human commands, intuit human desires, and predict human intentions resulting in a comfortable intelligent room for the human user.
Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems
"... Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to keep memory consistency from simultaneous accesses of bo ..."
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Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to keep memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target application: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we enable simultaneous accesses to different blocks and achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result that we achieve about 20-50 % performance gain compared to the base DPSDRAM architecture.
Dongwan Shin
, 2003
"... This report defines and describes a format for models of system components required for system-on-chip (SoC) design. In an SoC design process, starting from an initial system specification, an implementation of the system is created through a series of interactive and automated steps by gradually sy ..."
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This report defines and describes a format for models of system components required for system-on-chip (SoC) design. In an SoC design process, starting from an initial system specification, an implementation of the system is created through a series of interactive and automated steps by gradually synthesizing and assembling a system design using components taken out of a set of databases. Generally, databases are needed for processing elements (PEs), bus and other communication protocols, and RTL units. In this report we aim to provide an exhaustive list of requirements for components in an automated SoC design flow using the example of a concrete database format. Following a description of the basic database format in general, this report defines the format of each of the three databases in detail. Using information in this report, specific database formats for diverse SoC design flows can be developed. Specifically, the database format in this report is used successfully in our SoC Design Environment, SCE.
