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A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
 IEEE Transactions on VLSI Systems
, 2003
"... In deep submicron and nanometer designs for battery driven portable applications, the minimization of total energy, average power, peak power, and peak power differential are equally important. In this paper, we propose a framework for simultaneous reduction of these energy and transient power compo ..."
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Cited by 17 (11 self)
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In deep submicron and nanometer designs for battery driven portable applications, the minimization of total energy, average power, peak power, and peak power differential are equally important. In this paper, we propose a framework for simultaneous reduction of these energy and transient power components during behavioral synthesis. A new parameter called "Cycle Power Profile Function" (CPF) is defined which captures the transient power characteristics as a weighted sum of mean cycle power and mean cycle differential power. Minimizing this parameter using multiple voltages and dynamic clocking results in reduction of both energy and transient power. Based on the above, a datapath scheduling algorithm called "CPFScheduler " is developed which attempts to minimize the CPF. Experimental results show that for two voltage levels, three operating frequencies, switching activity of 0.5 and power profiling factor of 0.5, the scheduler achieves (i) total energy reductions in the range of 27 53%, (ii) average power reductions in the range of 40 73% (iii) peak power reductions in the range of 58 78% and (iv) peak power differential reductions in the range of 60 97%. Further, the impact of switching, profiling factor and resource constraints on the power profile is studied in detail.
Energy Efficient Scheduling for Datapath Synthesis
 In Proceedings of the International Conference on VLSI Design
, 2003
"... In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and resource constrained, utilize the concepts of multiple supply voltage and dynamic clocking for energy minimization. In dyna ..."
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Cited by 10 (8 self)
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In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and resource constrained, utilize the concepts of multiple supply voltage and dynamic clocking for energy minimization. In dynamic clocking, the functional units can be operated at different frequencies depending on the computations occurring within the datapath during a given clock cycle. The strategy is to schedule high energy units, such as the multipliers at lower frequencies such that they can be operated at lower voltages to reduce energy consumption and the low energy units, such as adders at higher frequencies, to compensate for speed. The algorithms have been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that for the time constrained algorithm, energy savings in the range of 3375% are obtained. Similarly, for resource constrained algorithm, under various resource constraints using two supply voltage levels (5.0V,3.3V ), energy savings in the range of 24 53% can be obtained.
Peak Power Minimization through Datapath Scheduling
 in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Feb 2003
, 2003
"... In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while th ..."
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Cited by 8 (4 self)
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In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels average peak power reduction around and average PDP reduction of can be obtained. For the MVMC scheme, average peak power reduction is around and average PDP reduction is , for similar resource constraints.
Simultaneous Peak and Average Power Minimization During Datapath Scheduling
, 2005
"... In low power design for deep submicron and nanometer regimes, the peak power, power fluctuation, average power and total energy are equally design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power. The minimization schemes ..."
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Cited by 6 (3 self)
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In low power design for deep submicron and nanometer regimes, the peak power, power fluctuation, average power and total energy are equally design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power. The minimization schemes based on integer linear programming (ILP) are developed for the design of datapaths that can function in three modes of operation: (1) single supply voltage and single frequency (SVSF), (2) multiple supply voltages and dynamic frequency clocking (MVDFC) and (3) multiple supply voltages and multicycling (MVMC). The techniques are evaluated by estimating the peak power consumption, the average power consumption and the power delay product of selected high level synthesis benchmark circuits for different resource constraints. Experimental results indicate that combining multiple supply voltages and dynamic frequency clocking, yields significant reductions in the peak power, the average power, and the power delay product.
Clock Power Reduction for Virtex5 FPGAs
 in Proceeding of the 17th ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, 2009
"... Clock network power in fieldprogrammable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R©VirtexTM5 FPGA are presented. The approaches are unique in that they leverage specific architectural aspects of Virtex5 to achieve reductions in ..."
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Cited by 4 (2 self)
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Clock network power in fieldprogrammable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R©VirtexTM5 FPGA are presented. The approaches are unique in that they leverage specific architectural aspects of Virtex5 to achieve reductions in dynamic power consumed by the clock network. The first approach comprises a placementbased technique to reduce interconnect resource usage on the clock network, thereby reducing capacitance and power (up to 12%). The second approach borrows the “clock gating ” notion from the ASIC domain and applies it to FPGAs. Clock enable signals on flipflops are selectively migrated to use the dedicated clock enable available on the FPGA’s builtin clock network, leading to reduced toggling on the clock interconnect and lower power (up to 28%). Power reductions are achieved without any performance penalty, on average.
Energy Efficient Datapath Scheduling using Multiple Voltages and Dynamic Clocking
 ACM Transactions on Design Automation of Electronic Systems (TODAES
, 2005
"... this paper, we consider the use of dynamic frequency clocking or frequency scaling alongwith multiple supply voltages for synthesis of low power datapath circuits useful for signal processing applications. In dynamic frequency clocking (hereto, will be referred to as DFC), the functional units could ..."
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Cited by 3 (2 self)
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this paper, we consider the use of dynamic frequency clocking or frequency scaling alongwith multiple supply voltages for synthesis of low power datapath circuits useful for signal processing applications. In dynamic frequency clocking (hereto, will be referred to as DFC), the functional units could operate at different speeds during each clock cycle depending on the units active in that cycle. We develop two new datapath scheduling algorithms, one referred to as TCDFC (time constrained) and other referred to as RCDFC (resource constrained), both of which aim at reducing energy consumption. The resource constraints consist of the number and type of each functional unit, the allowed voltages and frequencies. The time constraint is defined in terms of multiples of the critical path delay of the datapath circuit. RCDFC minimizes the total energy consumption of the datapath circuit by maximizing the utilization of lower supply voltage resources from the given sets of resources operating at different supply voltages while reducing the time penalty. On the other hand, TCDFC minimizes the total energy consumption of the datapath circuit without violating the timing constraints assuming that unlimited resources operating at different supply voltages are available. The scheduler will generate a parameter associated with each control step called clock frequency index, denoted as *+,/
ILP Models for Energy and Transient Power Minimization during Behavioral Synthesis
 in Proceedings of the 17th International Conference on VLSI Design
, 2004
"... The reduction of peak power, peak power differential, average power and energy are equally important in the design of lowpower battery driven portable applications. In this paper, we introduce a parameter called "cycle power function" (CPFDFC) that captures the above power characteristic ..."
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Cited by 3 (1 self)
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The reduction of peak power, peak power differential, average power and energy are equally important in the design of lowpower battery driven portable applications. In this paper, we introduce a parameter called "cycle power function" (CPFDFC) that captures the above power characteristics in the context of multiple supply voltage (MV) and dynamic frequency clocking (DFC) based designs. Further, we present ILP formulations for the minimization of CPFDFC during datapath scheduling. We conducted experiments on selected highlevel synthesis benchmarks for various resource constraints. Experimental results show that significant reduction in power, energy, and energy delay product, can be obtained using the proposed method.
Wireless Sensor Networks: A Survey on UltraLow PowerAware Design
"... Abstract—Distributed wireless sensor network consist on several scattered nodes in a knowledge area. Those sensors have as its only power supplies a pair of batteries that must let them live up to five years without substitution. That’s why it is necessary to develop some power aware algorithms that ..."
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Cited by 2 (0 self)
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Abstract—Distributed wireless sensor network consist on several scattered nodes in a knowledge area. Those sensors have as its only power supplies a pair of batteries that must let them live up to five years without substitution. That’s why it is necessary to develop some power aware algorithms that could save battery lifetime as much as possible. In this is document, a review of power aware design for sensor nodes is presented. As example of implementations, some resources and task management, communication, topology control and routing protocols are named.
An ILPBased Scheduling Scheme for Energy Efficient High Performance Datapath Synthesis
 in Proceedings of the International Symposium on Circuits and Systems
, 2003
"... In this paper, we describe an integer linear programming (ILP) based datapath scheduling algorithm which uses both multiple supply voltages and dynamic frequency clocking for power optimization. The scheduling technique assumes the number and type of different functional units as resource constraint ..."
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Cited by 2 (2 self)
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In this paper, we describe an integer linear programming (ILP) based datapath scheduling algorithm which uses both multiple supply voltages and dynamic frequency clocking for power optimization. The scheduling technique assumes the number and type of different functional units as resource constraints and minimizes the energy delay product (EDP). The energy savings directly comes from the use of multiple supply voltages and the performance improvement from dynamic frequency clocking. The algorithm has been applied to various high level synthesis benchmark circuits under different resource constraints. The experimental results show that under various resource constraints using two supply voltage levels , the average energy reduction is the average EDP reduction is .
ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis
, 2005
"... this paper, we propose an ILPbased framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called "modified cycle power function" (CPF ) is defined that captures the above power characteristics and facilitates integ ..."
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Cited by 2 (0 self)
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this paper, we propose an ILPbased framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called "modified cycle power function" (CPF ) is defined that captures the above power characteristics and facilitates integer linear programming formulations. The ILPbased datapath scheduling schemes with CPF as objective function are developed assuming three modes of datapath operation, such as, single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). We conducted experiments on selected highlevel synthesis benchmark circuits for various resource constraints and estimated power, energy and energy delay product for each of them. Experimental results show that significant reductions in power, energy and energy delay product can be obtained. Categories and Subject Descriptors: B.5.1 [RegisterTransferLevel Implementation]: Datapath Design; B.5.2 [RegisterTransferLevel Implementation]: Automatic Synthesis, Optimization; G.1.6 [Numerical Analysis]: Optimization, Integer Programming General Terms: Algorithms, Performance, Design, Reliability, Linear Modeling of Nonlinearity, Scheduling Additional Key Words and Phrases: peak power, cycle difference power, peak power differential, average power, multiple supply voltages, dynamic frequency clocking, multicycling, datapath scheduling 1.