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An Exact Algorithm for the UniformlyOriented Steiner Tree Problem
 In Proceedings of the 10th European Symposium on Algorithms, Lecture Notes in Computer Science
, 2002
"... An exact algorithm to solve the Steiner tree problem for uniform orientation metrics in the plane is presented. The algorithm is based on the twophase model, consisting of full Steiner tree (FST) generation and concatenation, which has proven to be very successful for the rectilinear and Euclid ..."
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Cited by 18 (7 self)
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An exact algorithm to solve the Steiner tree problem for uniform orientation metrics in the plane is presented. The algorithm is based on the twophase model, consisting of full Steiner tree (FST) generation and concatenation, which has proven to be very successful for the rectilinear and Euclidean Steiner tree problems. By applying a powerful canonical form for the FSTs, the set of optimal solutions is reduced considerably.
Flexibility of Steiner trees in uniform orientation metrics
 NETWORKS
, 2004
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Hardness and approximation of octilinear Steiner trees
 IN PROCEEDINGS OF THE 16TH INTERNATIONAL SYMPOSIUM ON ALGORITHMS AND COMPUTATION (ISAAC 2005
, 2005
"... Given a point set K of terminals in the plane, the octilinear Steiner tree problem is to find a shortest tree that interconnects all terminals and edges run either in horizontal, vertical, or ±45 ◦ diagonal direction. This problem is fundamental for the novel octilinear routing paradigm in VLSI de ..."
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Cited by 2 (1 self)
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Given a point set K of terminals in the plane, the octilinear Steiner tree problem is to find a shortest tree that interconnects all terminals and edges run either in horizontal, vertical, or ±45 ◦ diagonal direction. This problem is fundamental for the novel octilinear routing paradigm in VLSI design, the socalled Xarchitecture. As the related rectilinear and the Euclidian Steiner tree problem are wellknown to be NPhard, the same was widely believed for the octilinear Steiner tree problem but left open for quite some time. In this paper, we prove the NPcompleteness of the decision version of the octilinear Steiner tree problem. We also show how to reduce the octilinear Steiner tree problem to the Steiner tree problem in graphs of polynomial size with the following approximation guarantee. We construct a graph of size O ( n2 ε2) which contains a (1+ε)–approximation of a minimum octilinear Steiner tree for every ε> 0 and n = K. Hence, we can apply any αapproximation algorithm for the Steiner tree problem in graphs (the currently best known bound is α ≈ 1.55) and achieve an (α + ε) approximation bound for the octilinear Steiner tree problem. This approximation guarantee also holds for the more difficult case where the Steiner tree has to avoid blockages (obstacles bounded by octilinear polygons).
A heuristic method for constructing hexagonal Steiner minimal trees for routing
 in VLSI”, Proc. of IEEE International Symposium on Circuits & Systems
, 2006
"... Abstract — In Deep submicron regime, interconnect delays dominate VLSI circuit design. Thus, construction of costeffective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M) routing architectures are currently being replaced by the di ..."
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Abstract — In Deep submicron regime, interconnect delays dominate VLSI circuit design. Thus, construction of costeffective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0 ◦,60 ◦ , and 120 ◦ oriented global and semiglobal wirings. Unlike the Xrouting, Yrouting is observed to support regular routing grid, which is important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Yrouting algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientation. I.
Minimum Congestion Placement for Yinterconnects: SOme studies and observations
 Proc. of IEEE CS International Symposium on VLSI
, 2007
"... Abstract — Yinterconnects for VLSI chips are based on the use of global and semiglobal wiring in only 0 ◦ , 60 ◦ , and 120 ◦. Though Xinterconnects are fast replacing the traditional Manhattan (M) interconnects, the very recently proposed Yinterconnects have been observed to possess certain key ..."
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Abstract — Yinterconnects for VLSI chips are based on the use of global and semiglobal wiring in only 0 ◦ , 60 ◦ , and 120 ◦. Though Xinterconnects are fast replacing the traditional Manhattan (M) interconnects, the very recently proposed Yinterconnects have been observed to possess certain key advantages. Yinterconnects tend to consume less routing resources than Minterconnects. Unlike the Xinterconnect architectures, Yinterconnect architectures support regular routing grid. This is indeed very important for simplifying manufacturing processes and applying the routing and design rule checking algorithms. Several efficient Yrouting algorithms have been proposed in literature. However, to the best of our knowledge, not much have been reported so far in designing algorithms for Yinterconnectbased VLSI module placement and its effects on the congestion or wirelengths. In this paper, in an attempt to fill the gap in the existing literature, we propose a novel simulatedannealingbased placement technique for mixedsized cells which tries to reduce the congestion for Yinterconnects. The proposed method attempts to reduce the congestion, and observes the corresponding changes in the estimated lengths of the Yinterconnects. It has been implemented in Linux environment and experiments performed with randomly generated instances, and some wellknown benchmarks. The wirelength estimates for the Yinterconnects, and Manhattan interconnects for the same placement instances are compared. Results obtained are quite encouraging. The experimental results for a specific number of iterations and cooling schedule show improvements in congestion in most of the cases. I.
On some selected issues in VLSI Interconnect Layouts in the nanometer range
, 2008
"... The advent of deep submicron and nanometric regime for CMOS semiconductor technology has resulted in several restrictions in the physical design of VLSI circuits primarily through constraints imposed by interconnects. These constraints typically include the interconnect delay, congestion, crosstal ..."
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The advent of deep submicron and nanometric regime for CMOS semiconductor technology has resulted in several restrictions in the physical design of VLSI circuits primarily through constraints imposed by interconnects. These constraints typically include the interconnect delay, congestion, crosstalk, power dissipation and others. These issues have to be considered in the physical design of VLSI circuits. For a specific set of design goals, faster design convergence is often achieved by considering estimates of some or all of these parameters in the physical synthesis and logic synthesis stages. Thus, accurate estimation of these parameters have direct impact on issues such as convergence, performance, yield and manufacturability of chips, and there is immense scope of research in design and performance of interconnects. In addition to these, efforts are on for exploration and use of routing architectures which are different from the traditional Manhattan architecture. In this survey, we attempt to provide a brief overview of some of the select areas of the stateofthe art research on interconnect routing in the deep submicron and nanometer range.
Rotationally Optimal Spanning and Steiner Trees in Uniform Orientation Metrics
, 2003
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Approximation of Octilinear Steiner Trees Constrained by Hard and Soft Obstacles
, 2006
"... The novel octilinear routing paradigm (Xarchitecture) in VLSI design requires new approaches for the construction of Steiner trees. In this paper, we consider two versions of the shortest octilinear Steiner tree problem for a given point set K of terminals in the plane: (1) a version in the presenc ..."
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The novel octilinear routing paradigm (Xarchitecture) in VLSI design requires new approaches for the construction of Steiner trees. In this paper, we consider two versions of the shortest octilinear Steiner tree problem for a given point set K of terminals in the plane: (1) a version in the presence of hard octilinear obstacles, and (2) a version with rectangular soft obstacles. The interior of hard obstacles has to be avoided completely by the Steiner tree. In contrast, the Steiner tree is allowed to run over soft obstacles. But if the Steiner tree intersects some soft obstacle, then no connected component of the induced subtree may be longer than a given fixed length L. This kind of length restriction is motivated by its application in VLSI design where a large Steiner tree requires the insertion of buffers (or inverters) which must not be placed on top of obstacles. For both problem types, we provide reductions to the Steiner tree problem in graphs of polynomial size with the following approximation guarantees. Our main results are (1) a 2–approximation of the octilinear Steiner tree problem in the presence of hard rectilinear or octilinear obstacles which can be computed in O(n log 2 n) time, where n denotes the number of obstacle vertices plus the number of terminals, (2) a (2 + ε)–approximation of the octilinear Steiner tree problem in the presence of soft rectangular obstacles which runs in O(n 3) time, and (3) a polynomial time (1.55 + ε)– approximation of the octilinear Steiner tree problem in the presence of soft rectangular obstacles.