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25
Fixedoutline Floorplanning: Enabling Hierarchical Design
 IEEE Trans. on VLSI
, 2003
"... Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixedoutline floorplan formulation that is more relevant t ..."
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Cited by 113 (10 self)
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Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixedoutline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixedoutline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported [28]. A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet1 that can operate in both outlinefree and fixedoutline modes. We use Parquet1 to floorplan a design, with approximately 32000 cells, in 37 min using a topdown, hierarchical paradigm.
Fixedoutline Floorplanning Through Better Local Search
 IN PROC. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN
, 2001
"... Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, ..."
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Cited by 56 (4 self)
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Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work,
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation
, 2000
"... of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e. ..."
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Cited by 33 (3 self)
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of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e. to translate the sequence pair to its corresponding block placement. This paper presents a new approach to evaluate a sequence pair based on computing longest common subsequence in a pair of weighted sequences. We present a very simple and problem. We also show that using a more sophisticated in [1]. For example, we achieve 60X speedup over the previous algorithm when input size n # ###.
Combinatorial Techniques for Mixedsize Placement
 ACM TRANS. ON DESIGN AUTOM. OF ELEC. SYS
, 2005
"... ..."
Slicing Floorplans with Boundary Constraint
 ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 18 Issue: 9
, 1999
"... In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These ..."
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Cited by 12 (2 self)
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In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a wellknown slicing floorplanner [10] to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solution in a simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good. 1. INTRODUCTION Floorplan design is an important step in physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to minimize total area and interconnec...
Slicing Floorplans With PrePlaced Modules
 In Proc. IEEE Int. Conf. on ComputerAided Design
, 1998
"... Existing floorplanners that use slicing floorplans are efficient in runtime and yet can pack modules tightly. However, none of them can handle preplaced modules. In this paper, we extend a wellknown slicing floorplanner [10] to handle preplaced modules. Our main contribution is a novel shape curve ..."
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Cited by 11 (2 self)
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Existing floorplanners that use slicing floorplans are efficient in runtime and yet can pack modules tightly. However, none of them can handle preplaced modules. In this paper, we extend a wellknown slicing floorplanner [10] to handle preplaced modules. Our main contribution is a novel shape curve computation procedure which can take the positions of the preplaced modules into consideration. The shape curve computation procedure is used repeatedly during the floorplanning process to fully exploit the shape flexibility of the modules to give a tight packing. Experimental results show that the extended floorplanner performs very well. 1 Introduction Floorplan design is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to minimize total area and interconnect cost. In this early stage of physical design, most of the modules are not yet designed and thus are flexible in shape (soft modules), some are completely de...
Handling Soft Modules in General Nonslicing Floorplan using Lagrangian Relaxation
"... In the early stage of floorplan design, many modules have large flexibilities in shape (soft modules). Handling soft modules in general nonslicing floorplan is a complicated problem. Many previous works have attempted to tackle this problem [12, 9, 8, 4] using heuristics or numerical methods but no ..."
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Cited by 11 (2 self)
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In the early stage of floorplan design, many modules have large flexibilities in shape (soft modules). Handling soft modules in general nonslicing floorplan is a complicated problem. Many previous works have attempted to tackle this problem [12, 9, 8, 4] using heuristics or numerical methods but none of them can solve it optimally and efficiently. In this paper, we show how this problem can be solved optimally by geometric programming using the Lagrangian relaxation technique. The resulting Lagrangian relaxation subproblem is so simple that the optimal size of each module can be computed in linear time. We implemented this method in a simulated annealing framework based on the sequence pair representation. The geometric program is invoked in every iteration of the annealing process to compute the optimal size of each module to give the best packing. The execution time is much faster (at least 15 times faster for data sets with more than 50 modules) than that of the most updated previous wor...
Floorplan Area Minimization using Lagrangian Relaxation
, 2000
"... Floorplan area minimization is an important problem because many modules have shape flexibilities during the floorplanning stage. Area minimization in general nonslicing floorplan is a complicated problem. Many previous works have attempted to tackle this problem [9; 6; 5; 1] using heuristics or nu ..."
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Cited by 10 (4 self)
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Floorplan area minimization is an important problem because many modules have shape flexibilities during the floorplanning stage. Area minimization in general nonslicing floorplan is a complicated problem. Many previous works have attempted to tackle this problem [9; 6; 5; 1] using heuristics or numerical methods but none of them can solve it optimally and efficiently. In this paper, we show how this problem can be solved optimally by a geometric programming using Lagrangian relaxation. The resulting Lagrangian relaxation subproblem is so simple that the size of each module can be found in constant time. We implemented our idea in a simulated annealing framework based on the sequence pair representation. The area minimization procedure is invoked in every iteration of the annealing process but the total execution time is still very much faster than that of the most updated previous work [4]. For a benchmark data with 49 modules, we take 19.5 hours using a 270 MHz Sun Ultra 5 while the...
Floorplan Sizing by Linear Programming Approximation
 in Proc. DAC, 2000
, 2000
"... In this paper, we present an approximation algorithm by linear programming(LP) for floorplan sizing problem. Given any topological constraints between blocks, we can formulate it as an LP problem with a cost function for the minimum bounding box area. Unlike slicing structures, this approach can han ..."
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Cited by 8 (0 self)
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In this paper, we present an approximation algorithm by linear programming(LP) for floorplan sizing problem. Given any topological constraints between blocks, we can formulate it as an LP problem with a cost function for the minimum bounding box area. Unlike slicing structures, this approach can handle any topological constraints as well as soft/hard/preplaced blocks, and timing constraints. Empirically, our method needs few iterations to find the optimum solution and shows one order of improvement over previous methods both in run time and capability to handle a larger problem size even on a very limited computing resource PC.
Integrated Power Supply Planning and Floorplanning
 In Proceedings IEEE Asia and South Pacific Design Automation Conference
, 2001
"... One of the most challenging issues in today’s highperformance VLSI design is to ensure highquality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored ..."
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Cited by 7 (2 self)
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One of the most challenging issues in today’s highperformance VLSI design is to ensure highquality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insufficient power supply for certain circuit blocks. In this paper, we present an optimal power supply planning algorithm based on network flow to shorten the current paths from power bumps to local power supply wirings. We have incorporated our algorithm into a floorplanning algorithm for integrated floorplanning and power supply planning. Experimental results are encouraging. 1.