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OnChip Interconnects for Next Generation SystemonChips
 In Proc. of the 15th Annual IEEE International ASIC/SOC Conference
, 2002
"... Today's deep submicron fabrication technologies enable design engineers to put an impressive number of components like microprocessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions of transistors can be integrated on one die and form a paralle ..."
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Today's deep submicron fabrication technologies enable design engineers to put an impressive number of components like microprocessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions of transistors can be integrated on one die and form a parallel system, consisting out of thousands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient onchip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers onto the design of SoCs and proposes an onchip architecture which is based on active switch boxes. We will show that this architecture is able to fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements.
A Compact Layout of the Butterfly
, 2003
"... For the Butterfly of N input/output vertices we present a layout on the rectilinear (square) grid of area 1/2 N² + o(N²). A lower bound of the same order is proved. The encompassing rectangle which defines the area is 45ffi slanted w.r.t. the grid axes and the input/output vertices are not on the b ..."
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Cited by 5 (2 self)
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For the Butterfly of N input/output vertices we present a layout on the rectilinear (square) grid of area 1/2 N² + o(N²). A lower bound of the same order is proved. The encompassing rectangle which defines the area is 45ffi slanted w.r.t. the grid axes and the input/output vertices are not on the boundary of this rectangle. The layout is componentscalable, i.e., if one allocates for each switch a square of a \Theta a area, the layout remains of area 1/2 N² + o(N²); that is, the value of a affects only the o(N²) term. The layout is also free of knockknees.
On the Physicl Layout of PRDTBased NoCs
"... In this paper, we present PRDT(2, 1), a new interconnection network topology for Networkonchip (NoC) design. PRDT(2,1) features a recursive structure, and has small diameter and average distance. We then focus our study on physical layout issues pertaining to PRDT(2, 1). Specifically, we show that ..."
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In this paper, we present PRDT(2, 1), a new interconnection network topology for Networkonchip (NoC) design. PRDT(2,1) features a recursive structure, and has small diameter and average distance. We then focus our study on physical layout issues pertaining to PRDT(2, 1). Specifically, we show that the minimum number of metal layers required for the placement and routing in a PRDT (2, 1)based NoC is 2. We further demonstrate that the routing channel widths can be dramatically reduced when more layers are available for layout purposes. This study confirms that PRDT(2, 1) is a practical and promising topology for onchip interconnection networks. 1.
On the VLSI Area and Bisection Width of Star Graphs and Hierarchical Cubic Networks
"... We solve an open question posed by Akers and Krishnamurthy in 1986 [1, 3] concerning VLSI layout of star graphs. We show that the area of the optimal layout of an Nnode star graph, hierarchical cubic network (HCN), or hierarchical foldedhypercube network (HFN) is N 2 =16 \Sigma o(N 2 ) under t ..."
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We solve an open question posed by Akers and Krishnamurthy in 1986 [1, 3] concerning VLSI layout of star graphs. We show that the area of the optimal layout of an Nnode star graph, hierarchical cubic network (HCN), or hierarchical foldedhypercube network (HFN) is N 2 =16 \Sigma o(N 2 ) under the Thompson model, or under the extended grid model where a node occupies a rectangle of sides that may range from n \Gamma 1 to o( p N) for the nstar, log 2 N + 1 to o( p N) for the HCN, and log 2 N + 2 to o( p N) for the HFN. An ndimensional star graph thus requires less area than any possible layout of a similarsize hypercube, but more than that of the much smaller ncube. We also derive multilayer layout for star graphs that has area N 2 8bL 2 =2c \Sigma o( N 2 L 2 ), where a node occupies a rectangle of sides ranging from d n\Gamma1 4 e to o( p N=L) and the number L of wiring layers satisfi es 2 L = o( p N=n). Finally we show that the bisection width of an Nnode star graph is N=4 \Sigma o(N) and the bisection width of an HCN or HFN is exactly N=4.
Nearly Optimal Three Dimensional Layout of Hypercube Networks ⋆
"... Abstract. In this paper we consider the threedimensional layout of hypercube networks. Namely, we study the problem of laying hypercube networks out on the threedimensional grid with the properties that all nodes are represented as rectangular slices and lie on two opposite sides of the bounding b ..."
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Abstract. In this paper we consider the threedimensional layout of hypercube networks. Namely, we study the problem of laying hypercube networks out on the threedimensional grid with the properties that all nodes are represented as rectangular slices and lie on two opposite sides of the bounding box of the layout volume. We present both a lower bound and a layout method providing an upper bound on the layout volume and the maximum wirelength of the hypercube network.