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Highly scalable algorithms for rectilinear and octilinear Steiner trees
 In Proc. Asian and South Pacific Design Automation Conf
, 2003
"... problem, which asks for a minimumlength interconnection of a given set of terminals in the rectilinear plane, is one of the fundamental problems in electronic design automation. Recently there has been renewed interest in this problem due to the need for highly scalable algorithms able to handle ne ..."
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problem, which asks for a minimumlength interconnection of a given set of terminals in the rectilinear plane, is one of the fundamental problems in electronic design automation. Recently there has been renewed interest in this problem due to the need for highly scalable algorithms able to handle nets with tens of thousands of terminals. In this paper we give a practical � heuristic for computing nearoptimal rectilinear Steiner trees based on a batched version of the greedy triple contraction algorithm of Zelikovsky [21]. Experiments conducted on both random and industry testcases show that our heuristic matches or exceeds the quality of best known RSMT heuristics, e.g., on random instances with more than 100 terminals our heuristic improves over the rectilinear minimum spanning tree by an average of 11%. Moreover, our heuristic has very well scaling runtime, e.g., it can route a 34kterminals net extracted from a real design in less than 25 seconds compared to over 86 minutes needed by the edgebased heuristic of Borah, Owens, and Irwin [3]. Since our heuristic is graphbased, it can be easily modified to handle practical considerations such as routing obstacles, preferred directions, via costs, and octilinear routing – indeed, experimental results show only a small factor increase in runtime when switching from rectilinear to octilinear routing. I.
Efficient MultiLayer ObstacleAvoiding Rectilinear Steiner Tree Construction
"... Abstract—Given a set of pins and a set of obstacles on routing layers, a multilayer obstacleavoiding rectilinear Steiner minimal tree (MLOARSMT) connects these pins by rectilinear edges within layers and vias between layers, and avoids running through any obstacle to construct a Steiner tree with ..."
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Abstract—Given a set of pins and a set of obstacles on routing layers, a multilayer obstacleavoiding rectilinear Steiner minimal tree (MLOARSMT) connects these pins by rectilinear edges within layers and vias between layers, and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The MLOARSMT problem is very important for many VLSI designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. Therefore, it is desired to develop an effective algorithm for the MLOARSMT problem. However, there is no existing work on this MLOARSMT problem. In this paper, we first formulate the MLOARSMT problem and identify key different properties of the problem from its singlelayer counterpart. Based on the multilayer obstacleavoiding spanning graph (MLOASG), we present the first algorithm to solve the MLOARSMT problem. Our algorithm can guarantee an optimal solution for any 2pin net and many higherpin nets. Experiments show that our algorithm results in 33 % smaller total costs on average than a constructionbycorrection heuristic which is widely used for Steinertree construction in the recent literature. I.
Minimum steiner tree construction
 IN ALPERT, C.J., MEHTA, D.P. AND SAPATNEKAR, S.S. (EDS), THE HANDBOOK OF ALGORITHMS FOR VLSI PHYSICAL DESIGN AUTOMATION
, 2009
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Viaaware global routing for good VLSI manufacturability and high yield
 in Proc. of ASAP 2005
"... CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called systemonachip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as ..."
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CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called systemonachip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering routability and wirelength constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wirelength. 1.
Computing the Stretch Factor of Paths, Trees, and Cycles in Weighted Fixed Orientation Metrics
"... Let G be a graph embedded in the L1plane. The stretch factor of G is the maximum over all pairs of distinct vertices p and q of G of the ratio L G 1 (p, q)/L1(p, q), where L G 1 (p, q) is the L1distance in G between p and q. We show how to compute the stretch factor of an nvertex path in O(n log ..."
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Let G be a graph embedded in the L1plane. The stretch factor of G is the maximum over all pairs of distinct vertices p and q of G of the ratio L G 1 (p, q)/L1(p, q), where L G 1 (p, q) is the L1distance in G between p and q. We show how to compute the stretch factor of an nvertex path in O(n log 2 n) worstcase time and O(n) space and we mention generalizations to trees and cycles, to general weighted fixed orientation metrics, and to higher dimensions. 1