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Reducing quasi-equal clocks in networks of timed automata
- In FORMATS
, 2012
"... Abstract. We introduce the novel notion of quasi-equal clocks and use it to improve the verification time of networks of timed automata. Intu-itively, two clocks are quasi-equal if, during each run of the system, they have the same valuation except for those points in time where they are reset. We p ..."
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Cited by 4 (3 self)
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Abstract. We introduce the novel notion of quasi-equal clocks and use it to improve the verification time of networks of timed automata. Intu-itively, two clocks are quasi-equal if, during each run of the system, they have the same valuation except for those points in time where they are reset. We propose a transformation that takes a network of timed au-tomata and yields a network of timed automata which has a smaller set of clocks and preserves properties up to those not comparing quasi-equal clocks. Our experiments demonstrate that the verification time in three transformed real world examples is much lower compared to the original. 1
Specification patterns can be formal and still easy
"... Abstract—Property specification is still one of the most challenging tasks for transference of software verification technology like model checking. The use of patterns has been proposed in order to hide the complicated handling of formal languages from the developer. However, this goal is not entir ..."
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Abstract—Property specification is still one of the most challenging tasks for transference of software verification technology like model checking. The use of patterns has been proposed in order to hide the complicated handling of formal languages from the developer. However, this goal is not entirely satisfied. When validating the pattern the developer may have to deal with the pattern expressed in some particular formalism. For this reason, we identify three desirable quality attributes for the underlying specification language: succinctness, ease of validation and modifiability. We show that typical formalisms such as temporal logics or automata fail at some extent to support these features. In this work we propose FVS, a graphical scenariobased language, as a possible alternative to specify behavioral properties. We illustrate FVS ’ features by describing one of the most commonly used pattern, the Response Pattern, and several variants of it. Other known patterns such as the Precedence pattern and the Constrained Chain pattern are also discussed. We also thoroughly compare FVS against other used approaches. I.
Behavioral modeling★
"... Abstract. Behavior needs to be understood from early stages of soft-ware development. In this context incremental and declarative modeling seems an attractive approach for closely capturing and analyzing re-quirements without early operational commitment. A traditional choice for such a kind of mode ..."
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Abstract. Behavior needs to be understood from early stages of soft-ware development. In this context incremental and declarative modeling seems an attractive approach for closely capturing and analyzing re-quirements without early operational commitment. A traditional choice for such a kind of modeling is a logic-based approach. Unfortunately, that might be turn out to be a low-level and particularly awkward mech-anism when dealing with event-based systems. In this work we present a scenario-based language for incrementally shaping the behavior of event-based systems. A notable feature of our notation are abstract auxiliary events that enable expressing arbitrary 휔-regular languages. The nota-tion is equipped with declarative semantics based on morphisms and a tableaux procedure is given to leverage on different types of automatic analysis. 1
