Results 1  10
of
14
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
 ACM Transactions on Design Automation of Electronic Systems (TODAES
, 2009
"... In highlevel synthesis for realtime embedded systems using heterogeneous functional units (FUs), it is critical to select the best FU type for each task. However, some tasks may not have fixed execution times. This article models each varied execution time as a probabilistic random variable and so ..."
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Cited by 14 (6 self)
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In highlevel synthesis for realtime embedded systems using heterogeneous functional units (FUs), it is critical to select the best FU type for each task. However, some tasks may not have fixed execution times. This article models each varied execution time as a probabilistic random variable and solves heterogeneous assignment with probability (HAP) problem. The solution of the HAP problem assigns a proper FU type to each task such that the total cost is minimized while the timing constraint is satisfied with a guaranteed confidence probability. The solutions to the HAP problem are useful for both hard realtime and soft realtime systems. Optimal algorithms are proposed to find the optimal solutions for the HAP problem when the input is a tree or a simple path. Two other algorithms, one is optimal and the other is nearoptimal heuristic, are proposed to solve the general problem. The experiments show that our algorithms can effectively reduce the total cost while satisfying timing constraints with guaranteed confidence probabilities. For example, our algorithms achieve an average reduction of 33.0 % on total cost with 0.90 confidence probability satisfying timing constraints compared with the previous work using worstcase scenario.
Allocation cost minimization for periodic hard realtime tasks in energyconstrained DVS systems
 In Proceedings of the 2006 IEEE/ACM International Conference on ComputerAided Design
, 2006
"... Energyefficiency and powerawareness for electronic systems have been important design issues in hardware and software implementations. We consider the scheduling of periodic hard realtime tasks along with the allocation of processors under a given energy constraint. Each processor type could be a ..."
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Cited by 8 (2 self)
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Energyefficiency and powerawareness for electronic systems have been important design issues in hardware and software implementations. We consider the scheduling of periodic hard realtime tasks along with the allocation of processors under a given energy constraint. Each processor type could be associated with its allocation cost. The objective of this work is to minimize the entire allocation cost of processors so that the timing and energy constraints are both satisfied. We develop approximation algorithms for processor types with continuous processor speeds or discrete processor speeds. The capability of the proposed algorithms was evaluated by a series of experiments, and it was shown that the proposed algorithms always derived solutions with system costs close to those of optimal solutions in the experiments. Keywords: Energyaware systems, Task scheduling, Realtime
Energy Minimization with Soft Realtime and DVS for Uniprocessor and Multiprocessor Embedded Systems £
"... Energysaving is extremely important in realtime embedded systems. Dynamic Voltage Scaling (DVS) is one of the prime techniques used to achieve energysaving. Due to the uncertainties in execution times of some tasks of systems, this paper models each varied execution time as a random variable. By ..."
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Cited by 4 (1 self)
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Energysaving is extremely important in realtime embedded systems. Dynamic Voltage Scaling (DVS) is one of the prime techniques used to achieve energysaving. Due to the uncertainties in execution times of some tasks of systems, this paper models each varied execution time as a random variable. By using probabilistic approach, we propose two optimal algorithms, one for uniprocessor and one for multiprocessor to explore soft realtime embedded systems and avoid overdesigning them. Our goal is to minimize the expected total energy consumption while satisfying the timing constraint with a guaranteed confidence probability. The solutions can be applied to both hard and soft realtime systems. The experimental results show that our approach achieves significant energysaving than previous work. 1
Efficient assignment with guaranteed probability for heterogeneous parallel dsp
 in Int’l Conference on Parallel and Distributed Systems (ICPADS
, 2006
"... In realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs), it is critical to select the best FU for each task. However, some tasks may not have fixed execution times. This paper models each varied execution time as a probabilistic random variable and solve ..."
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Cited by 3 (2 self)
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In realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs), it is critical to select the best FU for each task. However, some tasks may not have fixed execution times. This paper models each varied execution time as a probabilistic random variable and solves heterogeneous assignment with probability (HAP) problem. The solution of the HAP problem assigns a proper FU type to each task such that the total cost is minimized while the timing constraint is satisfied with a guaranteed confidence probability. The solutions to the HAP problem are useful for both hard realtime and soft realtime systems. Two algorithms, one is optimal and the other is heuristic, are proposed to solve the general problem. The experiments show that our algorithms can effectively reduce the total cost with guaranteed confidence probabilities satisfying timing constraints. For example, our algorithms achieve an average reduction of 33.5 % on total cost with 90 % confidence probability satisfying timing constraints compared with the previous work using worstcase scenario. 1
Optimal assignment with guaranteed confidence probability for trees on heterogeneous dsp systems
 in IASTED PDCS’05
, 2005
"... In realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs), it is critical to select the best FU for each task. However, some tasks may not have fixed execution times. This paper models each varied execution time as a probabilistic random variable and solve ..."
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Cited by 2 (1 self)
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In realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs), it is critical to select the best FU for each task. However, some tasks may not have fixed execution times. This paper models each varied execution time as a probabilistic random variable and solves heterogeneous assignment with probability (HAP) problem. The solutions to the HAP problem are useful for both hard real time and soft real time systems. We propose optimal algorithms for the HAP problem when the input is a tree or a simple path. The experiments show that our algorithms can effectively obtain the optimal solutions to simple paths and trees. For example, with our algorithms, we can obtain an average reduction of 32.5 % on total cost with 90 % confidence probability compared with the previous work using worstcase scenario.
LOOP SCHEDULING TO MINIMIZE COST WITH DATA MINING AND PREFETCHING FOR HETEROGENEOUS DSP
"... In realtime embedded systems, such as multimedia and video applications, cost and time are the most important issues and loop is the most critical part. Due to the uncertainties in execution time of some tasks, this paper models each varied execution time as a probabilistic random variable. We prop ..."
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Cited by 1 (0 self)
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In realtime embedded systems, such as multimedia and video applications, cost and time are the most important issues and loop is the most critical part. Due to the uncertainties in execution time of some tasks, this paper models each varied execution time as a probabilistic random variable. We proposes a novel algorithm to minimize the total cost while satisfying the timing constraint with a guaranteed confidence probability. First, we use data mining to predict the distribution of execution time and find the association rules between execution time and different inputs from history table. Then we use rotation scheduling to obtain the best assignment for total cost minimization, which is called the HAP problem in this paper. Finally, we use prefetching to prepare data in
unknown title
, 2007
"... www.elsevier.com/locate/jpdc Energyminimizationwith loop fusion andmultifunctionalunit scheduling formultidimensional DSP ..."
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www.elsevier.com/locate/jpdc Energyminimizationwith loop fusion andmultifunctionalunit scheduling formultidimensional DSP
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constrtaint with Guaranteed Probability
"... Low energy consumption is an important problem in realtime embedded systems and loop is the most energy consuming part in most cases. Due to the uncertainties in execution time of some tasks, this paper models each varied execution time as a probabilistic random variable. We use rotation scheduling ..."
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Low energy consumption is an important problem in realtime embedded systems and loop is the most energy consuming part in most cases. Due to the uncertainties in execution time of some tasks, this paper models each varied execution time as a probabilistic random variable. We use rotation scheduling and DVS (Dynamic Voltage Scaling) to minimize the expected total energy consumption while satisfying the timing constraint with a guaranteed confidence probability. Our approach can handle loops efficiently. In addition, it is suitable to both soft and hard realtime systems. And even for hard realtime, we have good results. 1
Mapping of Multiple Data Flow Graphs of DSP Applications onto ASIC/Reconfigurable Architectures
"... Abstract: This paper presents a novel technique for the mapping of set of DSP applications onto architectures targeting an ASIC/Reconfigurable implementation embedded on the same chip. Synthesis for such a hybrid implementation is carried out by developing a technique to partition the RTL structures ..."
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Abstract: This paper presents a novel technique for the mapping of set of DSP applications onto architectures targeting an ASIC/Reconfigurable implementation embedded on the same chip. Synthesis for such a hybrid implementation is carried out by developing a technique to partition the RTL structures corresponding to a set of DSP applications into a fixed base design part suitable for ASIC implementation and a nonbase design that varies with the applications and suitable for FPGA implementation. Experimental results reveal that the proposed scheme is efficient in exposing the hidden functional commonality in a set of RTL structures respecting some wellknown benchmark problems. We show through a set of test cases that our approach offers significant area saving relative to the stateoftheart.