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Task Execution Time Modeling for Heterogeneous Computing Systems
- Proc. Ninth Heterogeneous Computing Workshop (HCW ’00
, 2000
"... Abstract A distributed heterogeneous computing (HC) system consists of diversely capable machines harnessed together to execute a set of tasks that vary in their computation ..."
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Cited by 69 (2 self)
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Abstract A distributed heterogeneous computing (HC) system consists of diversely capable machines harnessed together to execute a set of tasks that vary in their computation
c ' TASK ASSIGNMENT HEURISTICS FOR PARALLEL A N D DISTRIBUTED CFD APPLICATIONS
"... Abstract. This paper proposes a task graph (TG) model to represent a single discrete step of multi-block overset grid computational fluid dynamics (CFD) applications. The TG model is then used to not only balance the computational workload across the overset grids but also t o reduce inter-grid comm ..."
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Cited by 1 (0 self)
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Abstract. This paper proposes a task graph (TG) model to represent a single discrete step of multi-block overset grid computational fluid dynamics (CFD) applications. The TG model is then used to not only balance the computational workload across the overset grids but also t o reduce inter-grid communication costs. We have developed a set of task assignment heuristics based on the constraints inherent in this class of CFD problems. Two basic assignments, the smallest task first (STF) and the largest task first (LTF), are first presented. They are then systematically costs. To predict the performance of the proposed task assignment heuristics, extensive performance evaluations are conducted on a synthetic TG with tasks defined in terms of the number of grid points in predetermined overlapping grids. A TG derived from a realistic problem with eight million grid points is also used as a test case. mhr3?_ce! +>, +egr;"2ti"x +e stll.73 cf Frccns:2g z-its &:'.e:7&rp:cpsz: ~ : :. ~ * ~ ~.: & ~ c ~ Key words. Overset grids, task graphs, performance prediction, parallel processing, high per-formance computing. AMS subject classifications. 05C90, 68U01, 65Y05 1. Introduction. The
Post-Placement Leakage Optimization for Partially Dynamically Reconfigurable FPGAs ∗
"... As technology continues to shrink, leakage power becomes an important issue for modern FPGAs. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGAs. We focus on eliminating leakage waste due to the delay between reconfiguration and task execution. We propose a post- ..."
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As technology continues to shrink, leakage power becomes an important issue for modern FPGAs. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGAs. We focus on eliminating leakage waste due to the delay between reconfiguration and task execution. We propose a post-placement leakage-aware scheduling algorithm that refines a placement generated by a performancedriven scheduler such that leakage waste is minimized and performance is not sacrificed. Experimental results on real and synthetic designs demonstrate the effectiveness and efficiency of our algorithm on leakage optimization.