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... bounds check computations also execute reliably. Rely does not require a specific underlying mechanism to execute these operations reliably; one can use any applicable software or hardware technique =-=[20, 26, 28, 51, 53, 57, 66, 70]-=-. To prevent the execution from taking control flow edges that are not in the program’s static control flow graph, Rely assumes that 1) instructions are stored, fetched, and decoded reliably (as is su...

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... nearthreshold operation to reduce the power required. Previous studies have shown a strong correlation between the increase in soft error rate and the decrease in device sizes and operating voltages =-=[9]-=-. This same study suggests that the soft error rate may reach very high levels, to the point that an undetected soft error may occur once per day in a single chip. The most insidious form of soft erro...

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...read-local duplication techniques such as EDDI [22] and SWIFT [26] redundantly execute instructions within a single thread, exploiting instruction level parallelism to improve performance. Shoestring =-=[11]-=- performs selective instruction duplication to achieve lower overhead than both EDDI and SWIFT, but at the cost of lower fault coverage. Redundant multi-threading techniques (e.g. SRMT [37] and DAFT [...

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...uptions are detected and, if not, to motivate detectors. This approach has been tried only for relatively small programs, however, because model checking is resource intensive. The Shoestring project =-=[45]-=- has developed a pure static analysis that identifies instructions where faults are likely to be detected quickly enough (e.g., there is a short path in the data-flow graph from such a fault to enough...

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...ion of fault equivalence for application fault sites (analogous to that of hardware fault equivalence). Section 5 describes the relationship with other work that has similar, but not identical, goals =-=[2, 6, 18, 23]-=-. 2. Fault Pruning Techniques Relyzer systematically analyzes all application fault sites and carefully selects a small subset for thorough fault injection experiments such that it can still estimate ...

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..., while the SER for logic is steadily rising. The aforementioned factors have motivated researchers to propose solutions to protect the microprocessor logic core against transient faults. Feng et al. =-=[9]-=- and Shivakumar et al. [29] presented data for the effect of device scaling on the failures in time (FIT1) metric. They showed an exponential increase in the SER for future technology generations. Sin...

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...rs by generating, storing, and checking the ECCs of only the registers with long lifetime. Blome et al. [12] proposes a register value cache that holds duplicates of live register values. Feng et al. =-=[13]-=- leverage the symptom based detection and selective instruction duplication to minimize user-visible failures induced by soft errors. Slick [14] avoids the redundancy for results predictable instructi...

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...proposals [35, 44, 49, 60, 67] typically insert redundant code into 3 a program at compile time or runtime, and check for transient faults at runtime. Among these proposals, compiler-based techniques =-=[44, 49, 60, 67, 12]-=- are only applicable to programs whose source codes are available. Separately compiled modules, such as libraries, cannot be protected using compiler-based techniques due to the absence of source code...

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... replicated rather than the entire pipeline. Given the trend that the data movement is consuming more power than the actual computation, duplex execution can save energy by only reading and writing data once while computing twice with them. 1Even though the detection is done at circuit-level, the technique in its entirety is discussed in the context of processor pipeline, hence belonging to this section. 11 Table 5: Comparison of detection techniques in software system. Overheads quoted from papers and not yet brought into Echelon’s context. TIMA [55] ED4I [54] SWIFT [56] SWAT [61] Shoestring [62] Replication Instruction Instruction Instruction None Some instruction Control flow check Yes No Yes Implicit Implicit Error types Hard, transient All Hard, transient All All Error coverage High High High Low Low Performance Overhead 200% 80% 41% 5-14% 16% Energy Overhead Roughly the same as performance overhead 4.3 Software Systems The main advantage of implementing error detection mechanisms in software is that it is not intrusive to the design and can be applied to most systems without modifying the underlying hardware structures. The most straightforward approaches in software have been re...

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... paths for an extended time before an observed failure (e.g., whole system crash). We further discuss the challenges of designing error tolerance techniques for the hypervisor. 1 Introduction In the era of warehouse-scale computing, a typical data center consists of hundreds of thousands of servers with multicore processors, multi-level caches, and a large amount of main memory. All these components - logical circuits in CPU, memory cells in cache and memory - are not immune to soft errors [1, 2]. Technology scaling already points to a projection of escalating soft error rates in future chips [3], which combined with high server count would result in shorter MTBF (mean time between failures) and require system-level techniques on fault prevention, detection, and recovery. On the other hand, virtualization has been widely adopted in large data centers to increase overall resource utilization. In a typical environment shown in Figure 1, a hypervisor provides an abstraction layer on top of hardware resources, working with privileged VM (e.g., Dom0 in Xen) to serve the requests from guest VMs (e.g., DomU). Note that the abstraction layer can consume a considerable amount of hardware resou...