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27
Simulationbased bug trace minimization with BMCbased refinement
 in Int’l Conf. on CAD, 2005
, 2007
"... Abstract—Finding the cause of a bug can be one of the most timeconsuming activities in design verification. This is particularly true in the case of bugs discovered in the context of a randomsimulationbased methodology, where bug traces, or counterexamples, may be several hundred thousand cycles ..."
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Abstract—Finding the cause of a bug can be one of the most timeconsuming activities in design verification. This is particularly true in the case of bugs discovered in the context of a randomsimulationbased methodology, where bug traces, or counterexamples, may be several hundred thousand cycles long. In this paper, BUg TRAce MINimization (Butramin), which is a bug trace minimizer, is proposed. Butramin considers a bug trace produced by a random simulator or semiformal verification software and produces an equivalent trace of shorter length. Butramin applies a range of minimization techniques, deploying both simulationbased and formal methods, with the objective of producing highly reduced traces that still expose the original bug. Butramin was evaluated on a range of designs, including the publicly available picoJava microprocessor, and bug traces up to one million cycles long. Experiments show that in most cases, Butramin is able to reduce traces to a very small fraction of their initial sizes, in terms of cycle length and signals involved. The minimized traces can greatly facilitate bug analysis and reduce regression runtime. Index Terms—Bug trace minimization (Butramin), counterexample minimization, error diagnosis, verification. I.
Introducing Binary Decision Diagrams in the ExplicitState Verification of Java Code
 Proc. Java Pathfinder Workshop
, 2011
"... One of the big performance problems of software model checking is the stateexplosion problem. Various tools exist to tackle this problem. One of such tools is Java Pathfinder (JPF) an explicitstate model checker for Java code that has been used to verify efficiently a number of real applications. ..."
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One of the big performance problems of software model checking is the stateexplosion problem. Various tools exist to tackle this problem. One of such tools is Java Pathfinder (JPF) an explicitstate model checker for Java code that has been used to verify efficiently a number of real applications. We present jpfbdd, a JPF extension that allows users to annotate Boolean variables in the system under test to be managed using Binary Decision Diagrams (BDDs). Our tool partitions the program states of the system being verified and manages one part using BDDs. It maintains a formula for the values of these state partitions at every point during the verification. This allows us to merge states that would be kept distinct otherwise, thereby reducing the effect of the stateexplosion problem. We demonstrate the performance improvement of our extension by means of three example programs including an implementation of the wellknown diningphilosophers problem. 1.
Distanceguided hybrid verification with GUIDO
 Proc. DATE, 2006
"... Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of highcoverage tests remains a major challenge even in light of this high performance ..."
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Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of highcoverage tests remains a major challenge even in light of this high performance. In this paper we present Guido, a hybrid verification software that uses formal verification techniques to guide the simulation towards a verification goal. Guido is novel in that 1) it guides the simulation by means of a distance function derived from the circuit structure, and 2) it has a trace sequence controller that monitors and controls the direction of the simulation by striking a balance between random chance and controlled hillclimbing. We present experimental results indicating that Guido can tackle complex designs, including a picoJava microprocessor, and reach a verification goal in far fewer simulation cycles than random simulation. 1.
Boolean Operations on Decomposed Functions
"... Disjoint support decompositions (DSDs) are a way of exposing the inherent hierarchical structure of a Boolean function. By decomposing a function in its disjoint support components it is possible to reduce its complexity by considering it as the simple composition of smaller blocks that are disjoint ..."
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Disjoint support decompositions (DSDs) are a way of exposing the inherent hierarchical structure of a Boolean function. By decomposing a function in its disjoint support components it is possible to reduce its complexity by considering it as the simple composition of smaller blocks that are disjoint, that is, they do not share any input variable. Exposing a function’s decomposability properties has the potential to enable optimizations in various application domains of computeraided design, from synthesis to verification. Moreover, it provides the potential for generating a compact representation of the function. Algorithms have been proposed that can decompose a function into a decomposition tree of the finest granularity components, once its Binary Decision Diagram (BDD) is given. However, no solutions have been suggested so far for applying Boolean operators directly on decomposed forms that do not require one to reconstruct first the BDD of the operand functions involved and then construct the BDD of the result. This paper proposes a novel algorithm to perform Boolean operations directly on a decomposed form. Our algorithm can construct complex DSDs by performing multiple Boolean operations directly on other simpler DSDs, without ever constructing the BDD of the functions. The implications of the contribution are twofold: 1) we can maintain a lower memory profile than previous algorithms generating DSDs as a consequence of not constructing the BDDs before decomposition, and 2) by using a decomposed form during Boolean function manipulation, it is possible to exploit directly the function’s hierarchical structure, exposed by the decomposed form, for further optimizations. We show results indicating that we always maintain a lower memory profile compared to previous decomposition techniques while achieving competitive runtime performance. We also show that our algorithm generates a representation of a Boolean function that can require significantly less memory than a BDD representation. Thus, our algorithm could provide a compact alternative to BDDs in memorycritical applications.
Automatic error correction of tristate circuits
 In Proceedings of the 17th IEEE Internation Conference on Computer Design (ICCD
, 1999
"... ..."
TEACHING HARDWARE DESCRIPTION AND VERIFICATION
"... Since 1999, the formal methods group of the Department of ..."
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Since 1999, the formal methods group of the Department of
Stålmarck’s Procedure 2.19 Reduced Ordered Binary Decision Diagrams (ROBDDs) 2.23 Sequential Circuits Verification 2.55 Relational Representation of FSMs 2.56 Relational Product of FSMs 2.60 Reachability Analysis on FSMs 2.62
"... XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two ..."
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XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two Boolean netlists, check if the corresponding outputs of the two circuits are equal for all possible inputs • Two circuits are equivalent iff the Boolean function representing the outputs of the networks are logically equivalent • Identify equivalence points and implications between the two circuits to simplify equivalence checking • Since a typical design proceeds by a series of local changes, in most cases there are many implications / equivalent subcircuits in the two circuits to be compared • Various tautology/satisfiability checking algorithms based on heuristics (problem is NPcomplete, but many work well on “real ” applications...) • In this course we consider three main combinational equivalence checking methods: Propositional resolution method (tautology/satisfiability checking) Stålmarck’s method (recent patented algorithm, very efficient and popular) ROBDDbased method (Boolean function converted into ROBDD’s representation)
Stålmarck’s Procedure 2.19 Reduced Ordered Binary Decision Diagrams (ROBDDs) 2.23 Sequential Circuits Verification 2.55 Relational Representation of FSMs 2.56 Relational Product of FSMs 2.60 Reachability Analysis on FSMs 2.62 Equivalence Checking Tools 2.
"... XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two ..."
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XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two Boolean netlists, check if the corresponding outputs of the two circuits are equal for all possible inputs • Two circuits are equivalent iff the Boolean function representing the outputs of the networks are logically equivalent • Identify equivalence points and implications between the two circuits to simplify equivalence checking • Since a typical design proceeds by a series of local changes, in most cases there are many implications / equivalent subcircuits in the two circuits to be compared • Various tautology/satisfiability checking algorithms based on heuristics (problem is NPcomplete, but many work well on “real ” applications...) • In this course we consider three main combinational equivalence checking methods: Propositional resolution method (tautology/satisfiability checking) Stålmarck’s method (recent patented algorithm, very efficient and popular) ROBDDbased method (Boolean function converted into ROBDD’s representation)
ABSTRACT DistanceGuided Hybrid Verification with GUIDO
"... Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of highcoverage tests remains a major challenge even in light of this high performance. ..."
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Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of highcoverage tests remains a major challenge even in light of this high performance. In this paper we present Guido, a hybrid verification software that uses formal verification techniques to guide the simulation towards a verification goal. Guido is novel in that 1) it guides the simulation by means of a distance function derived from the circuit structure, and 2) it has a trace sequence controller that monitors and controls the direction of the simulation by striking a balance between random chance and controlled hillclimbing. We present experimental results indicating that Guido can tackle complex designs, including a picoJava microprocessor, and reach a verification goal in far fewer simulation cycles than random simulation. 1.