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Independent Test Sequence Compaction through Integer Programming
 IN PROC. INTERNATIONAL CONF. COMPUTER DESIGN
, 2003
"... We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then solve through a wellknown method employing linear programming relaxation and randomized rounding. The key contribution of t ..."
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We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then solve through a wellknown method employing linear programming relaxation and randomized rounding. The key contribution of this approach is that it yields the first polynomial time approximation algorithm for this problem. More specifically, it provides a provably good approximation guarantee while running in time polynomial with respect to the number of vectors in the original test sequences and the number of faults. Another virtue of our approach is that it provides a lower bound for the compacted set of test sequences and, therefore, a quality measure for the test compaction algorithm. Experimental results on benchmark circuits demonstrate that the proposed solution efficiently identifies nearly optimal sets of compacted test sequences.
Static Compaction Using Overlapped Restoration and Segment Pruning
 in Proc. Intl. Conf. on ComputerAided Design
, 1998
"... : We propose a new technique for static compaction of test sequences. Our method is based on two key ideas: (1) overlapped vector restoration, and (2) identification, pruning, and reordering of segments. Overlapped restoration provides a significant computational advantage for large circuits. Segme ..."
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: We propose a new technique for static compaction of test sequences. Our method is based on two key ideas: (1) overlapped vector restoration, and (2) identification, pruning, and reordering of segments. Overlapped restoration provides a significant computational advantage for large circuits. Segments partition the compaction problem into subproblems. Segments are identified, dynamically pruned and reordered to achieve further compaction and speed up. When compared to the fastest method proposed in [8], our method was 5 to 30 times faster on ISCAS circuits and 20 to 50 times faster on large, industrial designs. The new algorithm was able to successfully process large industrial designs that could not be handled by earlier techniques [8] in 2 CPU days. I. Introduction Reduction in test set size can be achieved using static or dynamic test set compaction algorithms. Dynamic techniques [9, 10, 14, 15, 16] perform compaction concurrently with the test generation process. These techniq...
An Approach for Improving the Levels of Compaction Achieved by Vector Omission
 Int. Conf. on ComputerAided Design
, 1999
"... We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are used to reduce the lengths of test sequences for synchronous sequential circuits without reducing the fault coverage. Th ..."
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We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are used to reduce the lengths of test sequences for synchronous sequential circuits without reducing the fault coverage. The unique feature of the proposed approach is that test vectors omitted from the test sequence can be reintroduced at a later time. Reintroducing of vectors helps reduce the compacted test sequence length beyond the length that can be achieved if vectors are omitted permanently. Experimental results are presented to demonstrate the levels of compaction achieved by the sequence counting approach. 1.
Sequence reordering to improve the levels of compaction achievable by static compaction procedures,” Design Automation Test Eur
 Proceedings of the Conference on Design Automation and Test in Europe
, 2001
"... We describe a reordering procedure that changes the order of test vectors in a test sequence for a synchronous sequential circuit without reducing the fault coverage. We use this procedure to investigate the effects of reordering on the ability to compact the test sequence. Reordering is shown to ha ..."
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We describe a reordering procedure that changes the order of test vectors in a test sequence for a synchronous sequential circuit without reducing the fault coverage. We use this procedure to investigate the effects of reordering on the ability to compact the test sequence. Reordering is shown to have two effects on compaction. (1) The reordering process itself allows us to reduce the test sequence length. (2) Reordering can improve the effectiveness of an existing static compaction procedure. Reordering also provides an insight into the detection by test generation procedures of faults that are detected by relatively long subsequences. 1.
Accelerating the Compaction of Test Sequences in Sequential Circuits through Problem Size Reduction
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2003
"... The problem of compacting a set of test sequences for sequential circuits is modeled here with the help of a covering matrix, where the test sequences are modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults. From this formulati ..."
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The problem of compacting a set of test sequences for sequential circuits is modeled here with the help of a covering matrix, where the test sequences are modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults. From this formulation, reduction rules are extracted, particular to this type of problem which, iteratively applied, result in a significant reduction of the size of the initial compaction problem. A characteristic of the reduction rules is that their application will not compromise the optimum solution of the problem. The remaining reduced problem is then solved by a combination of a heuristic and an exact branch and bound algorithm. Experimental results using the above reduction rules show that the sizes of the given sets of test sequences are often significantly reduced and many times these rules directly produce the absolute minimum of the solution. The final results, compared with others from the literature and also with the absolute minima of the examples, computed separately, support the potential of the proposed approach.
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation
"... In this paper we present efficient Reverse Order Restoration (ROR) based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vectorbyvector faultsimulation based restoration of test subsequences, our technique restores test sequenc ..."
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In this paper we present efficient Reverse Order Restoration (ROR) based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vectorbyvector faultsimulation based restoration of test subsequences, our technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using State Traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques.
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
 Compaction of Sequential Circuits” Proc. Asian Test Sym
, 1998
"... We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) faultlist and testset partitioning, and (2) vector reordering. Typically, the first few vectors of a test set detect a large number of ..."
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We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) faultlist and testset partitioning, and (2) vector reordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that significant compaction can be achieved by partitioning faults into hard and easy faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second technique reorders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated reordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on sev...
REFERENCES
"... construction). The tradeoff coefficients α and β are used based on the importance of the two objectives. Here, we adjust the coefficients so that these two terms are approximately of equal weights. In fact, these two terms are tradeoff terms and are different in different test cases. In order not to ..."
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construction). The tradeoff coefficients α and β are used based on the importance of the two objectives. Here, we adjust the coefficients so that these two terms are approximately of equal weights. In fact, these two terms are tradeoff terms and are different in different test cases. In order not to bias one side, we choose a pair of α and β to balance the effects. Although we have observed a slight increase in I/O wirelength for “industry3 ” case containing many I/Oinvolved nets, we have obtained a better I/O timing performance by an averagely smaller I/O wirelength. V. C ONCLUSION In this paper, we have presented an I/O clustering step, considering DC and performance optimization for highend flipchip design. We formulate the problem as a mincost maximum flow problem, and the experimental results are encouraging. With a slight increase in the percentage of VDTV, we can automate the I/O buffer block generation, which, in turn, will yield an averagely better timing performance and a much less DC. ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for providing precious suggestions to greatly improve this paper.
Test Pattern Generation And Test Application Time Reduction Algorithms For VLSI Circuits
, 1999
"... As the complexity of VLSI circuits is increasing at the rate predicted by Moore's law and the switching frequencies are approaching a gigahertz, testing cost is becoming an important factor in the overall IC manufacturing cost. Testing cost is incurred by test pattern generation and test applic ..."
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As the complexity of VLSI circuits is increasing at the rate predicted by Moore's law and the switching frequencies are approaching a gigahertz, testing cost is becoming an important factor in the overall IC manufacturing cost. Testing cost is incurred by test pattern generation and test application processes. In this dissertation, we address both of these factors contributing to the testing cost. We propose new test pattern generation and test application time reduction algorithms for reducing the IC testing cost. We propose new efficient and robust structurebased techniques for speeding up the deterministic test pattern generation for combinational circuits. These techniques improve the averagecase performance of the PODEM algorithm by reducing number of backtracks with a low computational cost. We then extend these techniques to sequential circuits and propose new structurebased techniques for speeding up the deterministic test pattern generation for sequential circuits. These t...
Vector Generation using Spectral Methods
"... Two new test generation algorithms for combinational and sequential circuits have been proposed. Test vectors are generated using characteristic faults and spectral information embedded in a circuit under test (CUT) in the form of Hadamard coefficients for the circuits. The Hadamard coefficients are ..."
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Two new test generation algorithms for combinational and sequential circuits have been proposed. Test vectors are generated using characteristic faults and spectral information embedded in a circuit under test (CUT) in the form of Hadamard coefficients for the circuits. The Hadamard coefficients are extracted using input and output correlation for combinational circuits and using a test vectors targeted for a small set of faults in the circuits for sequential circuits often known as characteristic faults. 1.