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48
Implicit Test Generation for Behavioral VHDL Models
 Proceedings of International Test Conference
, 1998
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SimulationBased Techniques for Dynamic Test Sequence Compaction
 Proc. Int. Conf. ComputerAided Design
, 1996
"... Simulationbased techniques for dynamic compaction of test sequences are proposed. The first technique uses a fault simulator to remove test vectors from the partiallyspecified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, consid ..."
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Cited by 17 (4 self)
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Simulationbased techniques for dynamic compaction of test sequences are proposed. The first technique uses a fault simulator to remove test vectors from the partiallyspecified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in the partiallyspecified test sequence in order to increase the number of faults detected by the sequence. Significant reductions in test set sizes were observed for all benchmark circuits studied. Fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computationintensive deterministic test generator. 1 Introduction Deterministic test generators for single stuckat faults in sequential circuits typically target individual faults, and once a test is generated, the test is fault simulated t...
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
 in Proc. Conf. on Design Autom. and Test in Europe
, 1998
"... We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, ..."
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Cited by 14 (2 self)
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We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and retrial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compare...
Independent Test Sequence Compaction through Integer Programming
 IN PROC. INTERNATIONAL CONF. COMPUTER DESIGN
, 2003
"... We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then solve through a wellknown method employing linear programming relaxation and randomized rounding. The key contribution of t ..."
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Cited by 14 (0 self)
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We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then solve through a wellknown method employing linear programming relaxation and randomized rounding. The key contribution of this approach is that it yields the first polynomial time approximation algorithm for this problem. More specifically, it provides a provably good approximation guarantee while running in time polynomial with respect to the number of vectors in the original test sequences and the number of faults. Another virtue of our approach is that it provides a lower bound for the compacted set of test sequences and, therefore, a quality measure for the test compaction algorithm. Experimental results on benchmark circuits demonstrate that the proposed solution efficiently identifies nearly optimal sets of compacted test sequences.
Fast Algorithms For Static Compaction of Sequential Circuit Test Vectors
 in Proc. VLSI Test Symp
, 1997
"... Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently revisited throughout the application of a test set. Subsequences that ..."
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Cited by 13 (4 self)
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Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently revisited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states. I Introduction Test sequence compaction produces test sequences of reduced lengths, which can greatly reduce the test application time. Test application time is important because it directly impacts the cost of testing. Two types of compaction techniques exist: dynamic and static compaction. Dynamic test sequence compaction performs compaction concurrently with the te...
Efficient Spectral Techniques for Sequential ATPG
 Proc. IEEE DATE Conf
, 2001
"... We present a new test generation procedure for sequential circuits using spectral techniques. Iterative processes of filtering via compaction and spectral analysis of the filtered test set are performed for each primary input, extracting inherent spectral information embedded within the test sequenc ..."
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Cited by 13 (5 self)
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We present a new test generation procedure for sequential circuits using spectral techniques. Iterative processes of filtering via compaction and spectral analysis of the filtered test set are performed for each primary input, extracting inherent spectral information embedded within the test sequence. This information, when viewed in the frequency domain, reveals the characteristics of the input spectrum. The filtered and analyzed set of vectors is then used to predict and generate future vectors. We also developed a faultdropping technique to speed up the process. We show that very high fault coverages and small vector sets are consistently obtained in short execution times for sequential benchmark circuits. 1.
Bottleneck Removal Algorithm for Dynamic Compaction and Test Cycle Reduction
 in Proc. EURODAC
, 1995
"... ABSTRACT: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinational and sequential circuits. Several dynamic algorithms for compaction in combinational circuits have been proposed but, to the best of our knowledge, no dynamic method has been reported ..."
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Cited by 12 (2 self)
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ABSTRACT: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinational and sequential circuits. Several dynamic algorithms for compaction in combinational circuits have been proposed but, to the best of our knowledge, no dynamic method has been reported in the literature for compaction in non scan sequential circuits. Our algorithm is based on two key ideas: (1) we first identify bottlenecks that prevent vector compaction and test cycle reduction for test sequences generated thus far, and (2) future test sequences are generated with an attempt to eliminate bottlenecks of earlier generated test sequences. If all bottlenecks of a sequence are eliminated, then the sequence is dropped from the test set. The final test set generated by our algorithm is minimal in the following sense. Static vector compaction or test cycle reduction using setcovering or extended setcovering approaches (for example, reverse or any other order of fault simulation, with any specification of unspecified inputs in test sequences) cannot further reduce the number of vectors. Experimental results on scan and non scan sequential circuits are reported to demonstrate the effectiveness of our algorithm. 1.
Putting the Squeeze on Test Sequences
 Proc. Int. Test Conf
, 1997
"... Dynamic test sequence compaction is an e#ective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test ..."
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Cited by 11 (3 self)
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Dynamic test sequence compaction is an e#ective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test sequences provided by a test generator and previously evolved sequences already included in the test set are used as seeds in the genetic population. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches. I Introduction Considerable progress has been made in sequential circuit test generation for single stuckat faults [1][10]. Individual faults in a circuit are typically targeted, and once a test is generated to detect a targeted fault, the test is fault simulated to find all other faults detected by the test. In this way, the number of faults that must be specifically targeted by the automatic test generator (ATG...
Acceleration techniques for dynamic vector compaction
 in International Conference on ComputerAided Design
, 1995
"... ABSTRACT: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly improve the computation times without adversely affecting the quality of test sets that can be derived using st ..."
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Cited by 11 (2 self)
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ABSTRACT: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly improve the computation times without adversely affecting the quality of test sets that can be derived using stateoftheart compaction methods. Our techniques are based on three key ideas: (1) identification of supportsets, (2) target fault switching, and (3) use of dynamic equivalent and untestable fault analysis. All these techniques are useful in significantly reducing the number of faults that have to be considered by a test generator or a fault simulator in a dynamic vector compaction system. For fault simulation, support sets quickly identify a large subset of faults that are guaranteed to be undetectable by a given input sequence. For test generation, supportsets identify a large subsetof faults that are guaranteed to be undetectable by any extension of a partially specified test sequence. Experimental results on ISCAS 89 benchmark circuits and large production VLSI circuits are included. For full scan designs, our accelerationtechniques reducethe overall computation times by a factor of 2 to 3 without adversely affecting the quality (size) of the computed test sets or their fault coverages. The improvement factors obtained are higher for larger circuits. The acceleration techniques enabled the computation of compact test sets for large production circuits that the base test generation system was unable to process in more than 2 CPU days on a Silicon Graphics MIPS 4400 workstation. Results for sequential circuits also show that our acceleration techniques significantly improve the computation times for dynamic vector compaction. 1.
On Random Pattern Generation with the Selfish Gene Algorithm for Testing
 Digital Sequential Circuits,” in Proc. International Test Conf
, 2004
"... A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. We enhance the spectral method of sequential circuit test generation by using a SG algorithm. The objects ..."
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Cited by 10 (7 self)
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A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. We enhance the spectral method of sequential circuit test generation by using a SG algorithm. The objects of evolution are the Hadamard spectral matrix, nonlinear digital signal processing (DSP) filtering cutoff values, vector holding time, and relative input phase shifts, which are all modeled as genes. These characteristics, extracted from compacted test vectors, are used to create new vector sequences to be further compacted with higher fault coverage. Alternatively, new vectors were generated by holding randomly selected vectors and then randomly perturbing some bits in 8bit chunks of bit streams. Both the SG algorithm and holding with bitperturbation can outperform the previouslypublished spectral method in either fault coverage, or shorter vector length, or both. The SG algorithm is often superior to random bitperturbation but it requires more CPU time. 1