Architectural modification to enhance the floating-point performance of FPGAs (2008)

by MJ Beauchamp, S Hauck, KD Underwood, KS Hemmert
Venue:IEEE Dhandapani and Ramachandran EURASIP Journal on Image and Video Processing 2014, 2014:37 Page 15 of 15 http://jivp.eurasipjournals.com/content/2014/1/37Trans. Very Large Scale Integer (VLSI) Syst