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15
Twodimensional test data compression for scan-based deterministic
- BIST,” Proc. Int. Test Conf
, 2001
"... Abstract. In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To red ..."
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Abstract. In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility. Keywords: BIST, deterministic BIST, store and generate schemes, test data compression
Randomization based probabilistic approach to detect Trojan circuits
- in Proc. IEEE High Assurance Syst. Eng. Symp
"... Abstract-In this paper, we propose a randomization based technique to verify whether a manufactured chip conforms to its design or is infected by any trojan circuit. A trojan circuit can be inserted into the design or fabrication mask by a malicious manufacturer such that it monitors for a specific ..."
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Abstract-In this paper, we propose a randomization based technique to verify whether a manufactured chip conforms to its design or is infected by any trojan circuit. A trojan circuit can be inserted into the design or fabrication mask by a malicious manufacturer such that it monitors for a specific rare trigger condition, and then it produces a payload error in the circuit which alters the functionality of the circuit often causing a catastrophic crash of the system where the chip was being used. Since trojans are activated by rare input patterns, they are stealthy by nature and are difficult to detect through conventional techniques of functional testing. In this paper, we propose a novel randomized approach to probabilistically compare the functionality of the implemented circuit with the design of the circuit. Using hypothesis testing, we provide quantitative guarantees when our algorithm reports that there is no trojan in the implemented circuit. This allows us to trade runtime for accuracy. The technique is sound, that is, it reports presence of a trojan only if the implemented circuit is actually infected. If our algorithm finds that the implemented circuit is infected with a trojan, it also reports a fingerprint input pattern to distinguish the implemented circuit from the design. We illustrate the effectiveness of our technique on a set of infected and benign combinational circuits.
Efficient test compaction for pseudo-random testing
- in Proc. 14th Asian Test Symp
"... Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo-randomly. We propose an algorithm to find a small number of cube ..."
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Cited by 3 (0 self)
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Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo-randomly. We propose an algorithm to find a small number of cubes to cover all the test vectors, thus minimizing total test length. The test-cube finding algorithm repeatedly evaluates small perturbations of the current solution so as to maximize the expected test coverage of the cube. Experimental results show that our algorithm covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits. It outperforms comparable schemes reported in the literature.
Optimized Reseeding by Seed Ordering and Encoding
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, 2005
"... Abstract—Mixed-mode logic built-in self-test (BIST) applies bothpseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Eachscan-test cycle consists of: 1) shifting a test pattern into ..."
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Cited by 3 (2 self)
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Abstract—Mixed-mode logic built-in self-test (BIST) applies bothpseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Eachscan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern; and 3) shifting the captured response out of the scan chains. The shifting of the test pattern out of the scan chains is overlapped with shifting in the next test pattern. The pattern shifted into the scan chains comes from the output of the pseudorandom pattern generator (PRPG); this pattern is determined by the initial state or seed of the PRPG (the contents of the PRPG at the beginning of the shifting operation). In a pseudorandom cycle, the initial state is the final state (last PRPG contents) from the previous cycle. The initial state of a deterministic cycle is shifted into the PRPG either from an a tester or from an on-chip BIST controller. This paper describes techniques to minimize the number of deterministic seeds that must be used: the number of
Hidden Markov and Independence Models with Patterns for Sequential BIST
- 18TH IEEE VLSI TEST SYMPOSIUM
, 2000
"... We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence generator capable of reproducing the essential features of a set of precomputed deterministic test sequences. We use for thi ..."
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Cited by 1 (1 self)
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We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence generator capable of reproducing the essential features of a set of precomputed deterministic test sequences. We use for this purpose two new models called Hidden Markov Model with Patterns and Independence Model with Patterns. Compared to existing methods, the proposed technique exhibits a very high fault coverage, including performance testing, at the expense of a low silicon area overhead.
Low-Overhead Built-In BIST Reseeding
, 2002
"... ... In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The seeds are encoded in hardware. The seeds we use are deterministic so 100% fault coverage can be achieved. Our technique causes no performance overhead and does not change the origin ..."
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Cited by 1 (1 self)
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... In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The seeds are encoded in hardware. The seeds we use are deterministic so 100% fault coverage can be achieved. Our technique causes no performance overhead and does not change the original circuit under test. Compared to previous work our technique takes less area overhead. Also, the technique we present is applicable for single-stuck-at faults as well as transition faults. In our technique, we expand every seed to as many ATPG patterns as possible. This is different from many existing reseeding techniques that expand every seed into a single ATPG pattern. This paper presents the built-in reseeding algorithm together with the hardware synthesis algorithm and implementation for both single-stuck-at faults as well as transition faults
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
, 2001
"... Abstract. In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inve ..."
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Abstract. In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.
Hardware Trojan Detection for Gate-level ICs Using Signal Correlation Based Clustering
"... Abstract-Malicious tampering of the internal circuits of ICs can lead to detrimental results. Insertion of Trojan circuits may change system behavior, cause chip failure or send information to a third party. This paper presents an information-theoretic approach for Trojan detection. It estimates th ..."
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Abstract-Malicious tampering of the internal circuits of ICs can lead to detrimental results. Insertion of Trojan circuits may change system behavior, cause chip failure or send information to a third party. This paper presents an information-theoretic approach for Trojan detection. It estimates the statistical correlation between the signals in a design, and explores how this estimation can be used in a clustering algorithm to detect the Trojan logic. Compared with the other algorithms, our tool does not require extensive logic analysis. We neither need the circuit to be brought to the triggering state, nor the effect of the Trojan payload to be propagated and observed at the output. Instead we leverage already available simulation data in this informationtheoretic approach. We conducted experiments on the TrustHub benchmarks to validate the practical efficacy of this approach. The results show that our tool can detect Trojan logic with up to 100% coverage with low false positive rates.
54.3 Scan-BIST Based on Transition Probabilities
"... We demonstrate that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a fullscan circuit such that each test contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result we s ..."
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We demonstrate that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a fullscan circuit such that each test contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result we show that built-in test-pattern generation for scan circuits can be based on transition probabilities instead of probabilities of specific bits in the test set being 0 or 1. The resulting approach associates only two parameters with every set of test vectors: an initial value and a transition probability. We demonstrate that this approach is effective in detecting all the detectable single stuck-at faults in benchmark circuits.
Approved by:
, 2008
"... First and foremost, I would like to express my gratefulness to God for all his blessings. I am indebted to my advisor, Dr. Bharat L. Bhuva who has always been there to support, advice and direct me in my work. I can count the number of days that I have not been in his office without a question to as ..."
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First and foremost, I would like to express my gratefulness to God for all his blessings. I am indebted to my advisor, Dr. Bharat L. Bhuva who has always been there to support, advice and direct me in my work. I can count the number of days that I have not been in his office without a question to ask. He has been very patient with me and has always given me ideas when results were hard to come by. I would like to thank Dr.Massengill for his invaluable comments he offered for my research work. I would also like to thank Balaji Narasimham for his spontaneous help, especially at the beginning of my project. My special thanks also goes to Robert Shuler from NASA, JSC for helping me with my research work by fabricating my design. I would like to specially thank Daniel, Megan, Matt and Wole and also all the other members of the RER group for the help offered during the course of this work. I am also very thankful to all my professors for the time and effort they put into our weekly RER meetings to give valuable suggestions to students. My husband Mr.Vijay Chandramouli, has been my constant source of motivation, pushing me to strive harder and achieve more. He was always there for me,
