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35
Bounded model checking with QBF
 in Int’l Conf. on Theory and Applications of Satisfiability Testing
, 2005
"... Abstract. Current algorithms for bounded model checking (BMC) use SAT methods for checking satisfiability of Boolean formulas. These BMC methods suffer from a potential memory explosion problem. Methods based on the validity of Quantified Boolean Formulas (QBF) allow an exponentially more succinct r ..."
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Cited by 33 (1 self)
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Abstract. Current algorithms for bounded model checking (BMC) use SAT methods for checking satisfiability of Boolean formulas. These BMC methods suffer from a potential memory explosion problem. Methods based on the validity of Quantified Boolean Formulas (QBF) allow an exponentially more succinct representation of the checked formulas, but have not been widely used, because of the lack of an efficient decision procedure for QBF. We evaluate the usage of QBF in BMC, using generalpurpose SAT and QBF solvers. We also present a specialpurpose decision procedure for QBF used in BMC, and compare our technique with the methods using generalpurpose SAT and QBF solvers on reallife industrial benchmarks. Our procedure performs much better for BMC than the generalpurpose QBF solvers, without incurring the space overhead of propositional SAT. 1
Using SAT based image computation for reachability analysis
, 2003
"... 1 Introduction Image Computation and Reachability Analysis Computing the set ofstates reachable in one step from a given set of states under a transition relation forms the heart of many symbolic state exploration algorithms, includingreachability analysis, model checking [8, 6, 7], etc. This operat ..."
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Cited by 26 (5 self)
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1 Introduction Image Computation and Reachability Analysis Computing the set ofstates reachable in one step from a given set of states under a transition relation forms the heart of many symbolic state exploration algorithms, includingreachability analysis, model checking [8, 6, 7], etc. This operation is called image computation. Let us consider a state transition relation T over the set ofstates S. The set of states is defined by the set of valuations over a vector ofstate variables x. We denote a set or a vector of variables in a boldface. The
Achieving speedups in distributed symbolic reachability analysis through asynchronous computation
 In Correct Hardware Design and Verification Methods (CHARME
, 1995
"... Abstract. This paper presents a novel BDDbased distributed algorithm for reachability analysis which is completely asynchronous. Previous BDDbased distributed schemes are synchronous: they consist of interleaved rounds of computation and communication, in which the fastest machine (or one which i ..."
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Cited by 26 (1 self)
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Abstract. This paper presents a novel BDDbased distributed algorithm for reachability analysis which is completely asynchronous. Previous BDDbased distributed schemes are synchronous: they consist of interleaved rounds of computation and communication, in which the fastest machine (or one which is lightly loaded) must wait for the slowest one at the end of each round. We make two major contributions. First, the algorithm performs image computation and message transfer concurrently, employing nonblocking protocols in several layers of the communication and the computation infrastructures. As a result, regardless of the scale and type of the underlying platform, the maximal amount of resources can be utilized efficiently. Second, the algorithm incorporates an adaptive mechanism which splits the workload, taking into account the availability of free computational power. In this way, the computation can progress more quickly because, when more CPUs are available to join the computation, less work is assigned to each of them. Less load implies additional important benefits, such as better locality of reference, less overhead in compaction activities (such as reorder), and faster and better workload splitting. We implemented the new approach by extending a symbolic model checker from Intel. The effectiveness of the resulting scheme is demonstrated on a number of large industrial designs as well as public benchmark circuits, all known to be hard for reachability analysis. Our results show that the asynchronous algorithm enables efficient utilization of higher levels of parallelism. High speedups are reported, up to an order of magnitude, for computing reachability for models with higher memory requirements than was previously possible.
A novel SAT allsolutions solver for efficient preimage computation
 Proc. of Design, Automation and Test in Europe Conf
, 2004
"... In this paper, we present a novel allsolutions preimage SAT solver, SOLALL, with the following features: (1) a new successdriven learning algorithm employing smaller cut sets; (2) a marked CNF database nontrivially combining success/conflictdriven learning; (3) quantifiedjumpback dynamically q ..."
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Cited by 22 (0 self)
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In this paper, we present a novel allsolutions preimage SAT solver, SOLALL, with the following features: (1) a new successdriven learning algorithm employing smaller cut sets; (2) a marked CNF database nontrivially combining success/conflictdriven learning; (3) quantifiedjumpback dynamically quantifying primary input variables from the preimage; (4) improved free BDD built on the fly, saving memory and avoiding inclusion of PI variables; finally, (5) a practical method of storing all solutions into a canonical OBDD format. Experimental results demonstrated the efficiency of the proposed approach for very large sequential circuits. 1.
An efficient sequential SAT solver with improved search strategies
 in Proc. Des. Autom. and Test Eur
"... A sequential SAT solver Satori [1] was recently proposed as an alternative to combinational SAT in verification applications. This paper describes the design of SeqSAT – an efficient sequential SAT solver with improved search strategies over Satori. The major improvements include (1) a new and bet ..."
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Cited by 14 (3 self)
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A sequential SAT solver Satori [1] was recently proposed as an alternative to combinational SAT in verification applications. This paper describes the design of SeqSAT – an efficient sequential SAT solver with improved search strategies over Satori. The major improvements include (1) a new and better heuristic for minimizing the set of assignments to state variables, (2) a new prioritybased search strategy and a flexible sequential search framework which integrates different search strategies, and (3) a decision variable selection heuristic more suitable for solving the sequential problems. We present experimental results to demonstrate that our sequential SAT solver can achieve ordersofmagnitude speedup over Satori. We plan to release the source code of SeqSAT along with this paper. I.
Memory efficient allsolutions sat solver and its application for reachability analysis
 In Proceedings of the 5th International Conference on Formal Methods in ComputerAided Design (FMCAD
, 2004
"... Abstract. This work presents a memoryefficient AllSAT engine which, given a propositional formula over sets of important and nonimportant variables, returns the set of all the assignments to the important variables, which can be extended to solutions (satisfying assignments) to the formula. The e ..."
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Cited by 14 (1 self)
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Abstract. This work presents a memoryefficient AllSAT engine which, given a propositional formula over sets of important and nonimportant variables, returns the set of all the assignments to the important variables, which can be extended to solutions (satisfying assignments) to the formula. The engine is built using elements of modern SAT solvers, including a scheme for learning conflict clauses and nonchronological backtracking. Rediscovering solutions that were already found is avoided by the search algorithm itself, rather than by adding blocking clauses. As a result, the space requirements of a solved instance do not increase when solutions are found. Finding the next solution is as efficient as finding the first one, making it possible to solve instances for which the number of solutions is larger than the size of the main memory. We show how to exploit our AllSAT engine for performing image computation and use it as a basic block in achieving full reachability which is purely SATbased (no BDDs involved). We implemented our AllSAT solver and reachability algorithm using the stateoftheart SAT solver Chaff [19] as a code base. The results show that our new scheme significantly outperforms AllSAT algorithms that use blocking clauses, as measured by the execution time, the memory requirement, and the number of steps performed by the reachability analysis. 1
Efficient conflict analysis for finding all satisfying assignments of a boolean circuit
 In TACAS’05, LNCS 3440
, 2005
"... Abstract. Finding all satisfying assignments of a propositional formula has many applications to the synthesis and verification of hardware and software. An approach to this problem that has recently emerged augments a clauserecording propositional satisfiability solver with the ability to add “blo ..."
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Cited by 13 (3 self)
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Abstract. Finding all satisfying assignments of a propositional formula has many applications to the synthesis and verification of hardware and software. An approach to this problem that has recently emerged augments a clauserecording propositional satisfiability solver with the ability to add “blocking clauses. ” One generates a blocking clause from a satisfying assignment by taking its complement. The resulting clause prevents the solver from visiting the same solution again. Every time a blocking clause is added the search is resumed until the instance becomes unsatisfiable. Various optimization techniques are applied to get smaller blocking clauses, since enumerating each satisfying assignment would be very inefficient. In this paper, we present an improved algorithm for finding all satisfying assignments for a generic Boolean circuit. Our work is based on a hybrid SAT solver that can apply conflict analysis and implications to both CNF formulae and general circuits. Thanks to this capability, reduction of the blocking clauses can be efficiently performed without altering the solver’s state (e.g., its decision stack). This reduces the overhead incurred in resuming the search. Our algorithm performs conflict analysis on the blocking clause to derive a proper conflict clause for the modified formula. Besides yielding a valid, nontrivial backtracking level, the derived conflict clause is usually more effective at pruning the search space, since it may encompass both satisfiable and unsatisfiable points. Another advantage is that the derived conflict clause provides more flexibility in guiding the scorebased heuristics that select the decision variables. The efficiency of our new algorithm is demonstrated by our preliminary results on SATbased unbounded model checking of VIS benchmark models. 1
On subsumption removal and onthefly cnf simplification
 in: Proceedings of the International Conference on Theory and Applications of Satisfiability Testing (SAT’05), 2005
"... Abstract. Conjunctive Normal Form (CNF) Boolean formulas generated from resolution or solution enumeration often have much redundancy. It is desirable to have an efficient algorithm to simplify and compact such CNF formulas on the fly. Given a clause in a CNF formula, if a subset of its literals con ..."
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Cited by 12 (0 self)
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Abstract. Conjunctive Normal Form (CNF) Boolean formulas generated from resolution or solution enumeration often have much redundancy. It is desirable to have an efficient algorithm to simplify and compact such CNF formulas on the fly. Given a clause in a CNF formula, if a subset of its literals constitutes another clause in the formula, then the first clause is said to be subsumed by the second clause. A subsumed clause is redundant and can be removed from the original formula. In this paper, we present a novel algorithm to maintain a subsumptionfree CNF clause database by efficiently detecting and removing subsumption as the clauses are being added. Furthermore, we present an algorithm that compact the database greedily by recursively applying resolutions that decrement the size of the clause database. Our experimental evaluations show that these algorithms are efficient and effective in practice. 1
Advanced unbounded model checking based on aigs, bdd sweeping, and quantifier scheduling
 in Proceedings of the Conference on Formal Methods in Computer Aided Design (FMCAD). IEEE Computer Society Press, Nov 2006
"... Abstract — In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent years, we support unbounded model checking based on symbolic representations of characteristic functions. Among ..."
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Cited by 10 (5 self)
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Abstract — In this paper we present a complete method for verifying properties expressed in the temporal logic CTL. In contrast to the majority of verification methods presented in recent years, we support unbounded model checking based on symbolic representations of characteristic functions. Among others, our method is based on an advanced AndInverter Graph (AIG) implementation, quantifier scheduling, and BDD sweeping. For several examples, our method outperforms BDD based symbolic model checking by orders of magnitude. However, our approach is also able to produce competitive results for cases where BDD are known to perform well. I.
A SATbased algorithm for reparameterization in symbolic simulation
 In Proceedings of DAC 2004
, 2004
"... ABSTRACT Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one parametric representation to another smaller representation, in a process called reparameterization. For large circ ..."
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Cited by 9 (2 self)
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ABSTRACT Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one parametric representation to another smaller representation, in a process called reparameterization. For large circuits, the reparametrization step often results in a blowup of BDDs and is expensive due to a large number of quantifications of input variables involved. Efficient SAT solvers have been applied successfully for many verification problems. This paper presents a novel SATbased reparameterization algorithm that is largely immune to the large number of input variables that need to be quantified. We show experimental results on large industrial circuits and compare our new algorithm to both SATbased Bounded Model Checking and BDD based symbolic simulation. We were able to achieve on average 3x improvement in time and space over BMC and able to complete many examples that BDD based approach could not even finish.