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The entropy of FPGA reconfiguration
 IEEE Proceedings of International Conference on Field Programmable Logic and Applications (FPL). 2006. Pp
"... In line with Shannonâ€™s ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of ..."
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In line with Shannonâ€™s ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple offtheshelf compression techniques such as Golomb encoding and hierarchical vector compression achieve compression results that are within 110 % of the theoretical bound. We present an enhanced configuration memory system based on the hierarchical vector compression technique that accelerates reconfiguration in proportion to the amount of compression achieved. The proposed system demands little additional chip area and can be clocked at the same rate as the Virtex configuration clock. 1.