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M.: Classification of Dataflow Actors with Satisfiability and Abstract Interpretation
- International Journal of Embedded and Real-Time Communication Systems (IJERTCS
, 2012
"... Dataflow programming has been used to describe signal processing applications for many years, traditionally with cyclo-static dataflow (CSDF) or synchronous dataflow (SDF) models that restrict expressive power in favor of compile-time analysis and predictability. More recently, dynamic dataflow is b ..."
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Dataflow programming has been used to describe signal processing applications for many years, traditionally with cyclo-static dataflow (CSDF) or synchronous dataflow (SDF) models that restrict expressive power in favor of compile-time analysis and predictability. More recently, dynamic dataflow is being used for the description of multimedia video standards as promoted by the RVC standard (ISO/IEC 23001:4). Dynamic dataflow is not restricted with respect to expressive power, but it does require runtime scheduling in the general case, which may be costly to perform on software. We presented in a previous paper a method to automatically classify actors of a dynamic dataflow program within more restrictive dataflow models when possible, along with a method to transform the actors classified as static to improve execution speed by reducing the number of FIFO accesses (Wipliez and Raulet (2010)). This paper presents an extension of our classification method using satisfiability solving, and details the precise semantics used for the abstract interpretation of actors. Our extended classification is able to classify more actors than what could previously be achieved.
Memory bounds for the distributed execution of a hierarchical synchronous data-flow graph
- in SAMOS Proceedings
, 2012
"... Abstract—This paper presents an application analysis tech-nique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of devel-opment. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchron ..."
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Abstract—This paper presents an application analysis tech-nique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of devel-opment. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks. The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. State-of-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions. I.