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We explore the area efficiency of a class of stream-based dataflow architectures as a function of the grain-size, for a given set of applications. We believe the grain-size is a key parameter in balancing flexibility and efficiency of this class of architectures. We apply a clustering approach on a well-defined set of applications to derive a set of processing elements of varying grain-sizes. The resulting architectures are compared with respect to their silicon area. For a set of twenty-one industrially relevant video algorithms, we determined architectures with various grain-sizes. The results of this exercise indicate an improvement factor of two for the silicon area, while changing the grain-size from fine-grain to coarser-grain.

Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with stringent design constraints, the importance of hardware/software codesign methodologies increases steadily. Interfacing heterogeneous hardware and software components together through a communication structure is particularly error prone and time consuming. Hence, on the basis of a generic architecture dedicated to telecommunication and multimedia applications, we propose an extended communication synthesis method that provides characterization of communications and their implementation schemes in the target architecture. This method takes place after the partitioning and scheduling phase and may constitute the basis of a back-end of a codesign framework leading to HW/SW integration.

. We explore the area efficiency of a class of stream-based dataflow architectures as a function of the grain-size, for a given set of applications. We believe the grain-size is a key parameter in balancing flexibility and efficiency of this class of architectures. We apply a clustering approach on a well-defined set of applications to derive a set of processing elements of varying grain-sizes. The resulting architectures are compared with respect to their silicon area. For a set of twenty-one industrially relevant video algorithms, we determined architectures with various grain-sizes. The results of this exercise indicate an improvement factor of two for the silicon area, while changing the grain-size from fine-grain to coarser-grain. 1. Introduction The change from analog to digital video signal processing allows the integration of many complex digital functions in a single television set. The challenge is to come up with a cost efficient signal processing architecture in terms of ...