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62
On Static Compaction of Test Sequences for Synchronous Sequential Circuits",
- 33rd Design Autom. Conf.,
, 1996
"... Abstract We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences onl ..."
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Cited by 48 (8 self)
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Abstract We propose several compaction procedures for synchronous sequential circuits based on test vector restoration. Under a vector restoration procedure, all or most of the test vectors are first omitted from the test sequence. Test vectors are then restored one at a time or in subsequences only as necessary to restore the fault coverage of the original sequence. Techniques to speed-up the restoration process are investigated. These include limiting the test vectors initially omitted from the test sequence, consideration of several faults in parallel during restoration, and the use of a parallel fault simulator.
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
- Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers
, 2000
"... The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simul ..."
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Cited by 21 (8 self)
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The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by highlevel constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.
Automatic Test Pattern Generation for Functional RTL Circuits Using Assignment Decision Diagrams
- Proc. of ACM/IEEE DAC
, 2000
"... In this paper, we present an algorithm for generating test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. To do this we utilize a data structure named assignment decision diagram which has bee ..."
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Cited by 21 (1 self)
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In this paper, we present an algorithm for generating test patterns automatically from functional register transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level. To do this we utilize a data structure named assignment decision diagram which has been proposed previously in the field of high level synthesis. The advent of RTL synthesis tools have made functional RTL designs widely popular. This paper addresses the problem of test pattern generation directly at this level due to a number of advantages inherent at the RTL. Since the number of primitive elements at the RTL is usually lesser than the logic level, the problem size is reduced leading to a reduction in the test generation time over logic-level ATPG. A reduction in the number of backtracks can lead to improved fault coverage and reduced test application time over logic-level techniques. The test patterns thus generated can also be used to perform RTL-RTL and RTL-logic validation. The algorithm is very versatile and can tackle almost any type of single-clock design though performance varies according to the design style. It gracefully degrades to an inefficient logic-level ATPG algorithm if it is applied to a logic-level circuit. Experimental results demonstrate that over 1000 times reduction in test generation time can be achieved by this algorithm on certain types of RTL circuits without any compromise in fault coverage.
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
- in Proc. Conf. on Design Autom. and Test in Europe
, 1998
"... We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, ..."
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Cited by 14 (2 self)
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We extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compare...
Peak power estimation using genetic spot optimization for large VLSI circuits
- IEEE DATE
, 1999
"... Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power po ..."
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Cited by 13 (1 self)
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Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7 % tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times. I
Putting the Squeeze on Test Sequences
- Proc. Int. Test Conf
, 1997
"... Dynamic test sequence compaction is an e#ective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test ..."
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Cited by 11 (3 self)
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Dynamic test sequence compaction is an e#ective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test sequences provided by a test generator and previously evolved sequences already included in the test set are used as seeds in the genetic population. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches. I Introduction Considerable progress has been made in sequential circuit test generation for single stuck-at faults [1]--[10]. Individual faults in a circuit are typically targeted, and once a test is generated to detect a targeted fault, the test is fault simulated to find all other faults detected by the test. In this way, the number of faults that must be specifically targeted by the automatic test generator (ATG...
On Random Pattern Generation with the Selfish Gene Algorithm for Testing
- Digital Sequential Circuits,” in Proc. International Test Conf
, 2004
"... A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. We enhance the spectral method of sequential circuit test generation by using a SG algorithm. The objects ..."
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Cited by 10 (7 self)
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A selfish gene (SG) algorithm differs from the genetic algorithm (GA) because it evolves genes (characteristics) that provide higher fitness rather than evolving individuals with higher fitness. We enhance the spectral method of sequential circuit test generation by using a SG algorithm. The objects of evolution are the Hadamard spectral matrix, non-linear digital signal processing (DSP) filtering cutoff values, vector holding time, and relative input phase shifts, which are all modeled as genes. These characteristics, extracted from compacted test vectors, are used to create new vector sequences to be further compacted with higher fault coverage. Alternatively, new vectors were generated by holding randomly selected vectors and then randomly perturbing some bits in 8-bit chunks of bit streams. Both the SG algorithm and holding with bit-perturbation can outperform the previously-published spectral method in either fault coverage, or shorter vector length, or both. The SG algorithm is often superior to random bit-perturbation but it requires more CPU time. 1
Error Diagnosis of Sequential Circuits Using Region-Based Model
- IN PROC.OF IEEE VLSI DESIGN CONF
, 2001
"... Algorithms to locate multiple design errors using region-based model are studied for both combinational and sequential circuits. The model takes locality aspect of errors and is based on a 3-value, non-enumerative analysis technique. Studies show the e#ectiveness of the region based model for gate c ..."
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Cited by 9 (1 self)
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Algorithms to locate multiple design errors using region-based model are studied for both combinational and sequential circuits. The model takes locality aspect of errors and is based on a 3-value, non-enumerative analysis technique. Studies show the e#ectiveness of the region based model for gate connection and gate substitution errors. For sequential circuits, we try to locate the time frame at which the error was first excited, by re-simulating as few vectors as possible preceding the erroneous vector in a fully initialized circuit to carry out the diagnosis. Experimental results on benchmark circuits are used to demonstrate rapid and accurate locating of multiple errors.
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
- Proc. of the DATE Conf
, 1998
"... A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maxi ..."
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Cited by 9 (0 self)
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A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach. 1 Introduction Most recent work in the area of sequential circuit test generation has focused on the gate level and has been targeted at single stuck-at faults. Both deterministic fault-oriented and simulation-based approaches have been used e#ectively, although execution times are often long. The key factor limiting the e#ciency of these approaches has been the lack of knowledge about circuit behavior. Architectural-level test generation has been proposed as a means ...
Hybrid Fault Simulation for Synchronous Sequential Circuits
, 1999
"... We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation - three-valued, symbolic and mixed - are supported. W ..."
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Cited by 9 (4 self)
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We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation - three-valued, symbolic and mixed - are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for th...
