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Heterogenous Simulation -- mixing discrete-event model with dataflow
, 1996
"... This paper relates to system-level design of signal processing systems, which are often heterogeneous in implementation technologies and design styles. The heterogeneous approach, by combining small, specialized models of computation, achieves generality and also lends itself to automatic synthesis ..."
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Cited by 19 (4 self)
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This paper relates to system-level design of signal processing systems, which are often heterogeneous in implementation technologies and design styles. The heterogeneous approach, by combining small, specialized models of computation, achieves generality and also lends itself to automatic synthesis and formal verification. Key to the heterogeneous approach is to define interaction semantics that resolve the ambiguities when different models of computation are brought together. For this purpose, we introduce a tagged signal model as a formal framework within which the models of computation can be precisely described and unambiguously differentiated, and their interactions can be understood. In this paper, we will focus on the interaction between dataflow models, which have partially ordered events, and discrete-event models, with their notion of time that usually defines a total order of events. A variety of interaction semantics, mainly in handling the different notions of time in the two models, are explored to illustrate the subtleties involved. An implementation based on the Ptolemy system from U.C. Berkeley is described and critiqued.
MCI-Multilanguage Distributed Co-Simulation Tool”, Chapter in Distributed and Parallel Embedded Systems, DIPES'98 organized by IFIP WG10.3/WG10.5, edited by F. Rammig
- In F. Rammig (Ed.), Distributed and Parallel Embedded Systems
, 1999
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Mixed Control/Data-Flow Representation For Modelling And Verification Of Embedded Systems
, 2002
"... Embedded system design issues become critical as implementation technologies evolve. The interaction between the control and data flow of an embedded system specification is an important consideration and, in order to cope with this aspect, a new internal design representation called Dual Flow Ne ..."
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Cited by 2 (0 self)
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Embedded system design issues become critical as implementation technologies evolve. The interaction between the control and data flow of an embedded system specification is an important consideration and, in order to cope with this aspect, a new internal design representation called Dual Flow Net (DFN) is introduced and further analysed in this thesis. One of the key features of this internal representation is its tight control and data flow interaction, which is achieved by means of two new concepts. Firstly, the structure of the new DFN model is formulated employing a tripartite graph as basis, which turns out to be advantageous for modelling heterogeneous systems. Secondly, a complex domain marking scheme is used to describe the behaviour of the system, leading to better results in terms of modelling the dynamics of the embedded system specification. Structural definitions, behavioural rules and graphical representation of the new DFN model is presented in this work. Besides the
Properties Coverification for HW/SW Systems
- proceedings of the international conference of Parallel and Distributed Processing Techniques and Applications (PDPTA’99), Las Vegas
, 1999
"... . The coverification of a given HW/SW system consists of checking whether the implementation of the software and hardware parts and their integration fulfill or not some or all the specification requirements of this system. In the case of a distributed model, the SW and HW system blocks are descr ..."
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Cited by 1 (0 self)
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. The coverification of a given HW/SW system consists of checking whether the implementation of the software and hardware parts and their integration fulfill or not some or all the specification requirements of this system. In the case of a distributed model, the SW and HW system blocks are described respectively by HLL (High Level Language) and HDL (Hardware Description Language) codes. When dealing with a unified model, both SW and HW components are implemented in the same language such as Java. In this paper, we propose a tool that allows designers to specify the properties of their systems in CPL (Coverification Properties description Language), and performs the coverification by simulation. The engine of this tool is implemented using the Java programming language and is mainly based on the management of threads. I. Introduction To avoid an eventual lengthy iterative codesign process of a given HW/SW system (that is often a result of an unsuccessful integration of hard...
Verification of an IP Interface Prototype Design through Simulation and Emulation
"... Abstract:- Designing contemporary Systems-On-a-Chip (SOCs) introduces increasing complexity and heterogeneity to integrated circuits. Attention has to be paid especially to the interfaces between the reusable Intellectual Property (IP) blocks used in them. We have previously presented our own interf ..."
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Abstract:- Designing contemporary Systems-On-a-Chip (SOCs) introduces increasing complexity and heterogeneity to integrated circuits. Attention has to be paid especially to the interfaces between the reusable Intellectual Property (IP) blocks used in them. We have previously presented our own interface solution called Heterogeneous IP Block Interconnection (HIBI). In this paper, the verification of a HIBI-based IP interface prototype design through simulation and emulation is discussed. The verification of the design is analysed and some performance characteristics from various steps of the verification flow are described. In addition to a significant reduction in compilation times, hardware emulation test runs are found to be hundreds of times faster than ordinary gate-level simulations. Nevertheless, both simulation and emulation were found to be needed in the verification process of modern SOC designs.
Experiences from Debugging a PCIX-based RDMA-capable NIC
"... Implementing and debugging high-performance newtork subsystems is a challenging task. In this paper, we present our experiences from developing and debugging a network interface card (NIC). Our NIC targets networked storage subsystems [17]. For this purpose it mainly provides support for remote dire ..."
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Implementing and debugging high-performance newtork subsystems is a challenging task. In this paper, we present our experiences from developing and debugging a network interface card (NIC). Our NIC targets networked storage subsystems [17]. For this purpose it mainly provides support for remote direct-memory-access (RDMA) write, sender-side notification of RDMA write completion, and receiver-side interrupt generation. In our work we examine issues that arise during system implementation and debugging, both in terms of correctness as well as performance. We present an analysis of the individual problems we encounter and we discuss how we address each case. For most problems we encounter, it is not possible to rely on existing debugging tools. However, we find that most of the techniques we use in this process, rely on collecting some form of event records from software or hardware components. We believe that such capabilities can be provided for independent hardware or software components in isolation, a fairly straight-forward task, thus, significantly simplifying the debugging process in complex systems of this nature. 1.
Lead Partner Southampton
, 2003
"... Version 1.0 The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability. ..."
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Version 1.0 The information in this document is provided as is and no guarantee or warranty is given that the information is fit for any particular purpose. The user thereof uses the information at its sole risk and liability.
Dissertação (mestrado) – Universidade Federal de Pernabuco.
"... A time Petri net based approach for software synthesis in Hard Real-Time embedded systems with multiple processors / Eduardo ..."
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A time Petri net based approach for software synthesis in Hard Real-Time embedded systems with multiple processors / Eduardo
