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High-Level Design Methodology for Ultra-Fast Software Defined Radio Prototyping on Heterogeneous Platforms
"... Abstract—The design of Software Defined Radio (SDR) equip-ments (terminals, base stations, etc.) is still very challenging. We propose here a design methodology for ultra-fast prototyping on heterogeneous platforms made of GPPs (General Purpose Processors), DSPs (Digital Signal Processors) and FPGAs ..."
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Abstract—The design of Software Defined Radio (SDR) equip-ments (terminals, base stations, etc.) is still very challenging. We propose here a design methodology for ultra-fast prototyping on heterogeneous platforms made of GPPs (General Purpose Processors), DSPs (Digital Signal Processors) and FPGAs (Field Programmable Gate Array). Lying on a component-based ap-proach, the methodology mainly aims at automating as much as possible the design from an algorithmic validation to a multi-processing heterogeneous implementation. The proposed methodology is based on the SynDEx CAD design approach, which was originally dedicated to multi-GPPs networks. We show how this was changed so that it is made appropriate with an embedded context of DSP. The implication of FPGAs is then addressed and integrated in the design approach with very little restrictions. Apart from a manual HW/SW partitioning, all other operations may be kept automatic in a heterogeneous processing context. The targeted granularity of the components, which are to be assembled in the design flow, is roughly the same size as that of a FFT, a filter or a Viterbi decoder for instance. The re-use of third party or pre-developed IPs is a basis for this design approach. Thanks to the proposed design methodology it is possible to port “ultra ” fast a radio application over several platforms. In addition, the proposed design methodology is not restricted to SDR equipment design, and can be useful for any real-time embedded heterogeneous design in a prototyping context. Index Terms—Software-defined radio, design methodology, heterogeneous platform, cross-layer design I.
The Impact of Aging on an FPGA-based Physical Unclonable Function
"... are emerging as a powerful security primitive that can potentially solve several security problems. A PUF needs to be robust against reversible as well as irreversible temporal changes in circuits. While the effect of the reversible temporal changes on PUFs is well studied, it is equally important t ..."
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are emerging as a powerful security primitive that can potentially solve several security problems. A PUF needs to be robust against reversible as well as irreversible temporal changes in circuits. While the effect of the reversible temporal changes on PUFs is well studied, it is equally important to analyze the effect of the irreversible temporal changes i.e. aging on PUFs. In this work, we perform an accelerated aging testing on an FPGA-based ring oscillator PUF (RO-PUF) and analyze how it affects the functionality of the PUF. Based on our experiment using a group of 90-nm Xilinx FPGAs, we observe that aging makes PUF responses unreliable. On the other hand, the randomness of PUF responses remains unaffected despite aging. Keywords-Physical Unclonable Function; aging; FPGA; I.
Security in Embedded Systems
"... Security in embedded systems is limited due to resource constraints. Security in embedded systems have to be adapted to these limitations. We provide a brief look at some of the limitations, such as the battery- and processor-gap. We also discuss some solutions to the limitations. In most systems th ..."
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Security in embedded systems is limited due to resource constraints. Security in embedded systems have to be adapted to these limitations. We provide a brief look at some of the limitations, such as the battery- and processor-gap. We also discuss some solutions to the limitations. In most systems the solutions are based on specialized cryptographic auxiliary processors. However there are other solutions that are more efficient but not as widely used. Two of the other solutions are the instruction-and data-driver approaches which requires hardware support. We also look at the impact of the faster growth rate of the Shannon-Hartley theorem compared to Moore's law. 1.
Towards Implementing a Fully Wireless
"... Eliminating all wires is the next technological challenge in making the electrocardiograph compact and wearable to the point where it can be used for continuous monitoring of mobile patients, athletes and soldiers in the field. In this paper the main challenges to overcome when removing wires are di ..."
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Eliminating all wires is the next technological challenge in making the electrocardiograph compact and wearable to the point where it can be used for continuous monitoring of mobile patients, athletes and soldiers in the field. In this paper the main challenges to overcome when removing wires are discussed, and emerging solutions of addressing them are presented. In addition, a novel top-level design integrating these emerging solutions is described. The design is currently being prototyped.
Report of the symposium "Lernen, Wissen, Adaptivität 2011 " of the GI special interest groups KDML, IR and WM.
, 2011
"... This Technical Report is the collection of papers that have been submitted to the Workshops of the symposium "Lernen, Wissen, Adaptivität 2011 " of the GI special interest groups KDML, IR and WM. All rights remain with the respective authors. Editors: ..."
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This Technical Report is the collection of papers that have been submitted to the Workshops of the symposium "Lernen, Wissen, Adaptivität 2011 " of the GI special interest groups KDML, IR and WM. All rights remain with the respective authors. Editors:
A Systematic Approach to Design an Efficient Physical Unclonable Function
, 2012
"... A Physical Unclonable Function (PUF) has shown a lot of promise to solve many security issues due to its ability to generate a random yet chip-unique secret in the form of an identifier or a key while resisting cloning attempts as well as physical tampering. It is a hardware-based challenge-response ..."
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A Physical Unclonable Function (PUF) has shown a lot of promise to solve many security issues due to its ability to generate a random yet chip-unique secret in the form of an identifier or a key while resisting cloning attempts as well as physical tampering. It is a hardware-based challenge-response function which maps its responses to its challenges exploiting complex statistical variation in the logic and interconnect inside integrated circuits (ICs). An efficient PUF should generate a key that varies randomly from one chip to another. At the same time, it should reliably reproduce a key from a chip every time the key is requested from that chip. Moreover, a PUF should be robust to thwart any attack that aims to reveal its key. Designing an efficient PUF having all these qualities with a low cost is challenging. Furthermore, the efficiency of a PUF needs to be validated by characterizing it over a group of chips. This is because a PUF circuit is supposed to be instantiated in several chips, and whether it can produce a chip-unique identifier/key or not cannot be validated using a single chip. The main goal of this research is to propose a systematic approach to build a random, reliable, and robust PUF incurring minimal cost. With this objective, we first formulate a novel PUF system model that uncouples PUF
1Time-bounded Authentication of FPGAs
"... Abstract—This paper introduces a novel technique to authen-ticate and identify field programmable gate arrays (FPGAs). The technique uses the reconfigurability feature of FPGAs to perform self-characterization and extract the unique timing of the FPGA building blocks over the space of possible input ..."
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Abstract—This paper introduces a novel technique to authen-ticate and identify field programmable gate arrays (FPGAs). The technique uses the reconfigurability feature of FPGAs to perform self-characterization and extract the unique timing of the FPGA building blocks over the space of possible inputs. The characterization circuit is then exploited for constructing a physically unclonable function (PUF). The PUF can accept different forms of challenges including pulse width, digital binary and placement challenges. The responses from the PUF are only verifiable by entities with access to the unique timing signature. However, the authentic device is the only entity who can respond within a given time constraint. The constraint is set by the gap between the speed of PUF evaluation on authentic hardware and simulation of its behavior. A suite of authentication protocols is introduced based on the time-bounded mechanism. We ensure that the responses are robust to fluctuations in operational conditions such as temperature and voltage variations by employing: (i) a linear calibration mechanism that adjusts the clock frequency by a feedback from on-chip temperature and voltage sensor readings, (ii) a differential PUF structure with real-valued responses that cancels out the common impact of variations on delays. Security against various attacks is discussed and a proof-of-concept implementation of signature extraction and authentication are demonstrated on Xilinx Virtex 5 FPGAs. Index Terms—field-programmable gate arrays; physically un-clonable function; delay characterization; time-bounded authen-tication; I.
