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37
A survey of hardware trojan taxonomy and detection
- IEEE Design & Test of Computers
"... design and fabrication process, ICs are becoming in-creasingly vulnerable to malicious activities and alter-ations. These vulnerabilities have raised serious concerns regarding possible threats to military sys-tems, financial infrastructures, transportation security, and household appliances. An adv ..."
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Cited by 76 (12 self)
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design and fabrication process, ICs are becoming in-creasingly vulnerable to malicious activities and alter-ations. These vulnerabilities have raised serious concerns regarding possible threats to military sys-tems, financial infrastructures, transportation security, and household appliances. An adversary can intro-duce a Trojan designed to disable or destroy a system at some future time, or the Trojan could leak confi-dential information and secret keys covertly to the ad-versary. Trojans can be implemented as hardware modifications to ASICs, commercial-off-the-shelf (COTS) parts, microprocessors, microcontrollers, net-work processors, or digital-signal processors (DSPs). They can also be implemented as firmware modifica-tions to, for example, FPGA bitstreams. These con-cerns have been documented in recent reports from
Physically unclonable functions: a study on the state of the art and future research directions
- in Towards Hardware-Intrinsic Security, Security and Cryptology
, 2010
"... The idea of using intrinsic random physical features to identify objects, sys-tems and people is not new. Fingerprint identification of humans dates at least back to the nineteenth century [20] and led to the field of biometrics. In the eighties and nineties of the twentieth century, random patterns ..."
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Cited by 45 (4 self)
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The idea of using intrinsic random physical features to identify objects, sys-tems and people is not new. Fingerprint identification of humans dates at least back to the nineteenth century [20] and led to the field of biometrics. In the eighties and nineties of the twentieth century, random patterns in pa-
Gate-Level Characterization: Foundations and Hardware Security Applications
, 2010
"... Gate-level characterization (GLC) is the process of characterizing each gate of an integrated circuit (IC) in terms of its physical and manifestation properties. It is a key step in the IC applications regarding cryptography, security, and digital rights management. However, GLC is challenging due t ..."
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Cited by 28 (14 self)
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Gate-level characterization (GLC) is the process of characterizing each gate of an integrated circuit (IC) in terms of its physical and manifestation properties. It is a key step in the IC applications regarding cryptography, security, and digital rights management. However, GLC is challenging due to the existence of manufacturing variability (MV) and the strong correlations among some gates in the circuit. We propose a new solution for GLC by using thermal conditioning techniques. In particular, we apply thermal control on the process of GLC, which breaks the correlations by imposing extra variations concerning gate level leakage power. The scaling factors of all the gates can be characterized by solving a system of linear equations using linear programming (LP). Based on the obtained gate level scaling factors, we demonstrate an application of GLC, hardware Trojan horse (HTH) detection, by using constraint manipulation. We evaluate our approach of GLC and HTH detection on several ISCAS85/89 benchmarks. The simulation results show that our thermally conditioned GLC approach is capable of characterizing all the gates with an average error less than the measurement error, and we can detect HTHs with 100 % accuracy on a target circuit.
FPGA PUF using Programmable Delay Lines
"... Abstract—This paper proposes a novel approach for efficient implementation of a real-valued arbiter-based physical unclonable function (PUF) on FPGA. We introduce a high resolution programmable delay logic (PDL) implemented by lookup table (LUT) internal structure. Using the PDL, we perform fine tun ..."
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Cited by 17 (6 self)
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Abstract—This paper proposes a novel approach for efficient implementation of a real-valued arbiter-based physical unclonable function (PUF) on FPGA. We introduce a high resolution programmable delay logic (PDL) implemented by lookup table (LUT) internal structure. Using the PDL, we perform fine tuning to cancel out delay skews caused by asymmetries in routing and systematic variations. We devise a symmetric switch structure that can be easily implemented on FPGA. To mitigate the arbiter metastability problem, we present and analyze methods for majority voting of responses. Lastly, a method to classify and group challenges into different robustness sets is introduced, to further increase the corresponding responses ’ stability in the face of environmental variations. Experimental evaluations show that the responses to robust challenges have an average error rate of less than 2 % under temperature variations from-10 o C to 75 o C. Index Terms—physical unclonable functions, programmable delay line, FPGA, majority voting, tuning I.
Security for volatile FPGAs
, 2009
"... With reconfigurable devices fast becoming complete systems in their own right, interest in their security properties has increased. While research on “FPGA sec-urity ” has been active since the early 2000s, few have treated the field as a whole, or framed its challenges in the context of the unique ..."
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Cited by 13 (0 self)
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With reconfigurable devices fast becoming complete systems in their own right, interest in their security properties has increased. While research on “FPGA sec-urity ” has been active since the early 2000s, few have treated the field as a whole, or framed its challenges in the context of the unique FPGA usage model and ap-plication space. This dissertation sets out to examine the role of FPGAs within a security system and how solutions to security challenges can be provided. I offer the following contributions. I motivate authenticating configurations as an additional capability to FPGA configuration logic, and then describe a flexible security protocol for remote recon-figuration of FPGA-based systems over insecure networks. Non-volatile memory devices are used for persistent storage when required, and complement the lack of features in some FPGAs with tamper proofing in order to maintain specified secur-ity properties. A unique advantage of the protocol is that it can be implemented on some existing FPGAs (i.e., it does not require FPGA vendors to add function-ality to their devices). Also proposed is a solution to the “IP distribution problem”
A Formal Foundation for the Security Features of Physical Functions
- IEEE SYMPOSIUM ON SECURITY AND PRIVACY
, 2011
"... Physical attacks against cryptographic devices typically take advantage of information leakage (e.g., side-channels attacks) or erroneous computations (e.g., fault injection attacks). Preventing or detecting these attacks has become a challenging task in modern cryptographic research. In this conte ..."
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Cited by 9 (2 self)
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Physical attacks against cryptographic devices typically take advantage of information leakage (e.g., side-channels attacks) or erroneous computations (e.g., fault injection attacks). Preventing or detecting these attacks has become a challenging task in modern cryptographic research. In this context intrinsic physical properties of integrated circuits, such as Physical(ly) Unclonable Functions (PUFs), can be used to complement classical cryptographic constructions, and to enhance the security of cryptographic devices. PUFs have recently been proposed for various applications, including anti-counterfeiting schemes, key generation algorithms, and in the design of block ciphers. However, currently only rudimentary security models for PUFs exist, limiting the confidence in the security claims of PUF-based security primitives. A useful model should at the same time (i) define the security properties
FPGA time-bounded unclonable authentication
- In Information Hiding 2010, volume 6387 of LNCS
, 2010
"... Abstract. This paper introduces a novel technique for extracting the unique tim-ing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and place ..."
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Cited by 8 (4 self)
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Abstract. This paper introduces a novel technique for extracting the unique tim-ing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and placement challenges can be built upon the delay signatures. We introduce a suite of new authentication protocols that take into account non-triviality of bitstream reverse-engineering in addition to the FPGA’s unprecedented speed in responding to challenges. Our technique is secure against various attacks and robust to fluctuations in opera-tional conditions. Proof of concept implementation of the signature extraction and evaluations of the proposed methods are demonstrated on Xilinx Virtex 5 FPGAs. Experimental results demonstrate practicality of the proposed techniques. 1
PUF Modeling Attacks on Simulated and Silicon Data
- IACR EPRINT
, 2013
"... Physical Unclonable Functions (PUFs) can be broken by numerical modeling attacks. Given a set of challenge-response pairs (CRPs) of a Strong PUF, our attacks construct a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs. This algorithm can subsequently impe ..."
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Cited by 6 (1 self)
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Physical Unclonable Functions (PUFs) can be broken by numerical modeling attacks. Given a set of challenge-response pairs (CRPs) of a Strong PUF, our attacks construct a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs. This algorithm can subsequently impersonate the PUF, and can be cloned and distributed arbitrarily. This breaks the security of almost all applications and protocols that are based on the respective PUF. The PUFs we attacked successfully include standard Arbiter PUFs and Ring Oscillator PUFs of arbitrary sizes, and XOR Arbiter PUFs, Lightweight Secure PUFs, and Feed-Forward Arbiter PUFs of up to a given size and complexity. The attacks are based upon various machine learning techniques, including a specially tailored variant of Logistic Regression and Evolution Strategies. Our results were obtained on a large number of CRPs coming from numerical simulations, as well as four million CRPs collected from FPGAs and ASICs. The performance on silicon CRPs is very close to simulated CRPs, confirming a conjecture from earlier versions of this work. Our findings lead to new design requirements for secure electrical PUFs, and will be useful to PUF designers and attackers alike.
Security Primitives and Protocols for Ultra Low Power Sensor Systems
"... Abstract — Security requirements in sensor systems include resiliency against physical and side-channel attacks, low energy for communication, storage, and computation, and the ability to realize a variety of public-key protocols. Furthermore, primitives and protocols that enable trusted remote oper ..."
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Cited by 6 (4 self)
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Abstract — Security requirements in sensor systems include resiliency against physical and side-channel attacks, low energy for communication, storage, and computation, and the ability to realize a variety of public-key protocols. Furthermore, primitives and protocols that enable trusted remote operation in terms of data, time, and location are essential to guarantee secure sensing. By integrating physically unclonable functions (PUFs) directly into sensor hardware and using device aging to securely match groups of sensors, we enable a variety of ultra low power security protocols for trusted remote sensing, including authentication and public key communication. I.
Securing Netlist-Level FPGA Design through Exploiting Process Variation and Degradation
"... The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high incentives to unauthorized cloning and reverse-engineering of ICs. Existing IC Digital Rights Management (DR ..."
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Cited by 5 (5 self)
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The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high incentives to unauthorized cloning and reverse-engineering of ICs. Existing IC Digital Rights Management (DRM) schemes often demands high overhead in area, power, and performance, or require non-volatile storage. Our goal is to develop a novel Intellectual Property (IP) protection technique that offers universal protection to both Application-Specific Integrated Circuits (ASIC) and Field-Programmable Gate-Arrays (FPGAs) from unauthorized manufacturing and reverse engineering. In this paper we show a proof-of-concept implementation of the basic elements of the technique, as well as a case study of applying the anti-cloning technique to a nontrivial FPGA design.
