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35
NineCoded Compression Technique for Testing Embedded Cores in SoCs
 IEEE TRANSACTIONS ON VLSI SYSTEMS
, 2005
"... This paper presents a new testdata compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in systemonchips and does not require any structural information of cores. The technique is flexible in utilizing both fixed and varia ..."
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This paper presents a new testdata compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in systemonchips and does not require any structural information of cores. The technique is flexible in utilizing both fixed and variablelength blocks. In spite of its simplicity, it provides significant reduction in testdata volume and testapplication time. The decompression logic is very small and can be implemented fully independent of the precomputed testdata set. Our technique is flexible and can be efficiently adopted for single or multiplescan chain designs. Experimental results for ISCAS’89 benchmarks illustrate the flexibility and efficiency of the proposed technique.
Adjustable width linear combinational scan vector decompression
 in Proc. Int. Conf. Comput.Aided Des. (ICCAD), 2003
"... A new scheme for combinational linear expansion is proposed for decompression of scan vectors. It has the capability to adjust the width of the linear expansion each clock cycle. This eliminates the requirement that every scan bitslice be in the output space of the linear decompressor. Depending on ..."
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Cited by 24 (4 self)
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A new scheme for combinational linear expansion is proposed for decompression of scan vectors. It has the capability to adjust the width of the linear expansion each clock cycle. This eliminates the requirement that every scan bitslice be in the output space of the linear decompressor. Depending on how specified the current bitslice is, the decompressor may load all scan chains or may load only a subset of the scan chains. This provides the nice feature that any scan vector can be generated using the proposed scheme regardless of the number or distribution of the specified bits. Thus, the proposed scheme allows the use of any ATPG procedure without any constraints. Moreover, it allows greater compression to be achieved than fixed width expansion techniques since the ratio of the number of scan chains to the number of tester channels can be scaled much larger. A procedure for designing and optimizing the adjustable width decompression hardware and obtaining the compressed data is described. Experimental data indicates that the proposed scheme is simple yet very effective. 1.
3Stage Variable Length ContinuousFlow Scan Vector Decompression Scheme
, 2004
"... This paper presents a 3stage continuousflow linear decompression scheme for scan vectors that uses a variable number of bits to encode each vector. By using 3stages of decompression, it can efficiently compress any test cube (i.e., deterministic test vector where the unassigned bit positions are ..."
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Cited by 24 (6 self)
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This paper presents a 3stage continuousflow linear decompression scheme for scan vectors that uses a variable number of bits to encode each vector. By using 3stages of decompression, it can efficiently compress any test cube (i.e., deterministic test vector where the unassigned bit positions are left as don't cares) regardless of the number of specified (care) bits. As a result of this feature, there is no need for any constraints on the automatic test generation process (ATPG) process. Any ATPG can be used with any amount of static or dynamic compaction. Experimental results are shown which demonstrate that the proposed scheme achieves extremely high encoding efficiency.
Ninecoded compression technique with application to reduced pincount testing and flexible onchip decompression
 Proc. IEEE/ACM Design, Automation and Test in Europe
, 2004
"... Abstract — This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and indep ..."
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Cited by 14 (2 self)
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Abstract — This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don’tcare bits unchanged in the compressed test set, and these bits can be filled randomly to detect nonmodeled faults. The proposed technique can be efficiently adopted for single or multiplescan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS’89 benchmarks illustrate the flexibility and efficiency of the proposed technique. I.
Restrict Encoding for Mixed–Mode BIST
 27TH IEEE VLSI TEST SYMPOSIUM
, 2009
"... Programmable mixed–mode BIST schemes combine pseudo–random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed–mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requ ..."
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Cited by 9 (7 self)
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Programmable mixed–mode BIST schemes combine pseudo–random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed–mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50 % hardware costs compared with the best schemes known so far while complete programmability is still preserved.
DeviationBased LFSR Reseeding for TestData Compression
"... Abstract—Linear feedback shift register (LFSR) reseeding forms the basis for many testcompression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased comp ..."
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Cited by 5 (0 self)
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Abstract—Linear feedback shift register (LFSR) reseeding forms the basis for many testcompression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuckat and transition faults derived from selected seeds for the ISCAS89 and the IWLS05 benchmark circuits. These patterns achieve higher coverage for transition and stuckopen faults than patterns obtained using other seedgeneration methods for LFSR reseeding. Given a pattern pair (p1,p2) for transition faults, we also examine the transitionfault coverage for launch on capture by using p1 and p2 to separately compute output deviations. Results show that p1 tends to be better when there is a high proportion of donotcare bits in the test cubes, while p2 is a more appropriate choice when the transitionfault coverage is high. Index Terms—Defect coverage, linear feedback shift register (LFSR) reseeding, output deviation, seed selection, test compression. I.
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion
"... The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The idea proposed in this paper is to use scan inversion to transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing the enc ..."
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Cited by 4 (2 self)
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The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The idea proposed in this paper is to use scan inversion to transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing the encoding efficiency while still keeping all the test cubes in the output space. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed method improves the encoding efficiency further. The key property used by the proposed method is that scan inversion is a linear transformation of the output space and thus the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize encoding efficiency. Experiments indicate that significant improvements in encoding efficiency can be achieved.
Improving linear test data compression
 IEEE TRANS. ON COMPUTERAIDED DESIGN
, 2006
"... The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping a ..."
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Cited by 4 (0 self)
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The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in the output space. Scan inversion is used to invert a subset of the scan cells while reconfiguration modifies the linear decompressor. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed methods improve the compression further. The key property of scan inversion is that it is a linear transformation of the output space and, thus, the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize compression. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for reconfiguring the linear decompressor. The proposed schemes can be utilized in various design flow scenarios and require no or very little hardware overhead. Experiments indicate that significant improvements in compression can be achieved.
Test Set Stripping Limiting the Maximum Number of Specified Bits
"... This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but exploits the information in the test set to quickly find test patterns with the desired properties. The resulting test sets sh ..."
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Cited by 4 (4 self)
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This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but exploits the information in the test set to quickly find test patterns with the desired properties. The resulting test sets show a significant reduction in the maximum number of specified bits in the test patterns. Furthermore, for commercial ATPG test sets even the overall number of specified bits is reduced substantially.
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
 in Proc. DATE 2008
"... We present a new type of Linear Feedback Shift Registers, ..."
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Cited by 4 (3 self)
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We present a new type of Linear Feedback Shift Registers,