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56
Efficient Seed Utilization for Reseeding based Compression
, 2003
"... ... reseeding architecture is the limited seed efficiency due to the variance in the number of specified bits per vector. This paper proposes a new LFSR reseeding architecture that essentially solves this problem, resulting in a significant compression ratio. The compression ratio is very close to t ..."
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Cited by 35 (3 self)
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... reseeding architecture is the limited seed efficiency due to the variance in the number of specified bits per vector. This paper proposes a new LFSR reseeding architecture that essentially solves this problem, resulting in a significant compression ratio. The compression ratio is very close to the entropy in terms of #total bits / #specified bits. The technique is applied on two industrial designs resulting in a compression ratio of 33x (with a seed efficiency of 95%), whereas the conventional reseeding architecture resulted in only 2x (with a seed efficiency of only 50%).
Packetbased Input Test Data Compression Techniques
 PROC. INT. TEST CONF
, 2002
"... This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The technique is based on grouping data packets and applying various binary encoding techniques, such as Huffman codes and GolombRi ..."
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Cited by 25 (0 self)
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This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The technique is based on grouping data packets and applying various binary encoding techniques, such as Huffman codes and GolombRice codes. Experiments on actual industrial designs and benchmark circuits show an input vector data reduction ranging from 17x to 70x.
Adjustable width linear combinational scan vector decompression
 in Proc. Int. Conf. Comput.Aided Des. (ICCAD), 2003
"... A new scheme for combinational linear expansion is proposed for decompression of scan vectors. It has the capability to adjust the width of the linear expansion each clock cycle. This eliminates the requirement that every scan bitslice be in the output space of the linear decompressor. Depending on ..."
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Cited by 24 (4 self)
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A new scheme for combinational linear expansion is proposed for decompression of scan vectors. It has the capability to adjust the width of the linear expansion each clock cycle. This eliminates the requirement that every scan bitslice be in the output space of the linear decompressor. Depending on how specified the current bitslice is, the decompressor may load all scan chains or may load only a subset of the scan chains. This provides the nice feature that any scan vector can be generated using the proposed scheme regardless of the number or distribution of the specified bits. Thus, the proposed scheme allows the use of any ATPG procedure without any constraints. Moreover, it allows greater compression to be achieved than fixed width expansion techniques since the ratio of the number of scan chains to the number of tester channels can be scaled much larger. A procedure for designing and optimizing the adjustable width decompression hardware and obtaining the compressed data is described. Experimental data indicates that the proposed scheme is simple yet very effective. 1.
3Stage Variable Length ContinuousFlow Scan Vector Decompression Scheme
, 2004
"... This paper presents a 3stage continuousflow linear decompression scheme for scan vectors that uses a variable number of bits to encode each vector. By using 3stages of decompression, it can efficiently compress any test cube (i.e., deterministic test vector where the unassigned bit positions are ..."
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Cited by 24 (6 self)
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This paper presents a 3stage continuousflow linear decompression scheme for scan vectors that uses a variable number of bits to encode each vector. By using 3stages of decompression, it can efficiently compress any test cube (i.e., deterministic test vector where the unassigned bit positions are left as don't cares) regardless of the number of specified (care) bits. As a result of this feature, there is no need for any constraints on the automatic test generation process (ATPG) process. Any ATPG can be used with any amount of static or dynamic compaction. Experimental results are shown which demonstrate that the proposed scheme achieves extremely high encoding efficiency.
Multilevel Huffman coding: An efficient testdata compression method for IP cores
 IEEE Trans. Comput.Aided Design Integr. Circuits Syst
, 2007
"... Abstract—A new testdata compression method suitable for cores of unknown structure is introduced in this paper. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Each Huffman codeword corresponds ..."
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Cited by 10 (2 self)
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Abstract—A new testdata compression method suitable for cores of unknown structure is introduced in this paper. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Each Huffman codeword corresponds to three different kinds of information, and thus, significant compression improvements compared to the already known techniques are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Moreover, the major part of the decompressor can be shared among different cores, which reduces the hardware overhead of the proposed architecture considerably. Additionally, the proposed technique offers increased probability of detection of unmodeled faults since the majority of the unknown values of the test sets are replaced by pseudorandom data generated by a linear feedback shift register. Index Terms—Embedded testing techniques, Huffman encoding, intellectual property (IP) cores, linear feedback shift registers (LFSRs), testdata compression. I.
Multiphase BIST: A new reseeding technique for high test data compression
 IEEE Trans. Comput.Aided Design Integr. Circuits Syst
, 2004
"... Abstract—In this paper, a new reseeding architecture for scanbased builtin selftest (BIST), which uses a linear feedback shift register (LFSR) as test pattern generator, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain of the circuit under test in differe ..."
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Cited by 9 (5 self)
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Abstract—In this paper, a new reseeding architecture for scanbased builtin selftest (BIST), which uses a linear feedback shift register (LFSR) as test pattern generator, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain of the circuit under test in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. A seedselection algorithm is furthermore presented that, taking advantage of the multiphase architecture, manages to significantly reduce the number of the required seeds for achieving complete (100%) fault coverage. The proposed technique can be used either in a full BIST implementation or in a testresource partitioning scenario, since the testdata storage requirements on the tester are very low. When a full BIST implementation is preferable, the multiphase architecture can also be combined with a dynamic reseeding scheme that uses combinational logic instead of a ROM in order to perform the reseedings. This way the implementation area of the BIST circuitry is further reduced. Experimental results demonstrate the advantages of the proposed LFSR reseeding approach over the already known reseeding techniques. Index Terms—Builtin selftest (BIST), logic circuit testing. I.
Achieving high Encoding Efficiency with partial dynamic LFSR Reseeding
 ACM Transactions on Design Automation of Electronic Systems
, 2004
"... Previous forms of LFSR reseeding have been static (i.e., test application is stopped while each seed is loaded) and have required full reseeding (i.e., the length of the seed is equal to the length of the LFSR). A new form of LFSR reseeding is described here that is dynamic (i.e., the seed is increm ..."
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Cited by 7 (0 self)
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Previous forms of LFSR reseeding have been static (i.e., test application is stopped while each seed is loaded) and have required full reseeding (i.e., the length of the seed is equal to the length of the LFSR). A new form of LFSR reseeding is described here that is dynamic (i.e., the seed is incrementally modified while test application proceeds) and allows partial reseeding (i.e. length of the seed is less than that of the LFSR). In addition to providing better encoding efficiency, partial dynamic LFSR reseeding has a simpler hardware implementation than previous schemes based on multiplepolynomial LFSRs.
Deterministic BIST Based on a Reconfigurable Interconnection
, 2003
"... We present a new approach for deterministic BIST in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase sh ..."
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Cited by 6 (0 self)
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We present a new approach for deterministic BIST in which a reconfigurable interconnection network (RIN) is placed between the outputs of a pseudorandom pattern generator and the scan inputs of the circuit under test (CUT). The RIN, which consists only of multiplexer switches, replaces the phase shifter that is typically used in pseudorandom BIST to reduce correlation between the test data bits that are fed into the scan chains. The connections between the LFSR and the scan chains can be dynamically changed (reconfigured) during a test session. In this way, the RIN is used to match the LFSR outputs to the test cubes in a deterministic test set. The control data bits used for reconfiguration ensure that all the deterministic test cubes are embedded in the test patterns applied to the CUT. The proposed approach requires very little hardware overhead, and fewer control bits compared to the storage required for reseeding techniques or for hybrid BIST. Moreover, as a nonintrusive BIST solution, it does not require any circuit redesign and has minimal impact on circuit performance.
DeviationBased LFSR Reseeding for TestData Compression
"... Abstract—Linear feedback shift register (LFSR) reseeding forms the basis for many testcompression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased comp ..."
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Cited by 5 (0 self)
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Abstract—Linear feedback shift register (LFSR) reseeding forms the basis for many testcompression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSRreseedingbased compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuckat and transition faults derived from selected seeds for the ISCAS89 and the IWLS05 benchmark circuits. These patterns achieve higher coverage for transition and stuckopen faults than patterns obtained using other seedgeneration methods for LFSR reseeding. Given a pattern pair (p1,p2) for transition faults, we also examine the transitionfault coverage for launch on capture by using p1 and p2 to separately compute output deviations. Results show that p1 tends to be better when there is a high proportion of donotcare bits in the test cubes, while p2 is a more appropriate choice when the transitionfault coverage is high. Index Terms—Defect coverage, linear feedback shift register (LFSR) reseeding, output deviation, seed selection, test compression. I.
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion
"... The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The idea proposed in this paper is to use scan inversion to transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing the enc ..."
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Cited by 4 (2 self)
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The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The idea proposed in this paper is to use scan inversion to transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing the encoding efficiency while still keeping all the test cubes in the output space. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed method improves the encoding efficiency further. The key property used by the proposed method is that scan inversion is a linear transformation of the output space and thus the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize encoding efficiency. Experiments indicate that significant improvements in encoding efficiency can be achieved.