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51
CorrelationAware Statistical Timing Analysis with NonGaussian Delay Distributions
 In DAC ’05: Proceedings of the 42nd annual conference on Design automation
, 2005
"... Process variations have a growing impact on circuit performance for today’s integrated circuit (IC) technologies. The NonGaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, we present an efficient blockba ..."
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Cited by 54 (0 self)
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Process variations have a growing impact on circuit performance for today’s integrated circuit (IC) technologies. The NonGaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, we present an efficient blockbased statistical timing analysis approach with linear complexity with respect to the circuit size, which can accurately predict NonGaussian delay distributions from realistic nonlinear gate and interconnect delay models. This approach accounts for all correlations, from manufacturing process dependence, to reconvergent circuit paths to produce more accurate statistical timing predictions. With this approach, circuit designers can have increased confidence in the variation estimates, at a low additional computation cost.
A General Framework for Accurate Statistical Timing Analysis Considering Correlations
 In DAC
, 2005
"... The impact of parameter variations on timing due to process and environmental variations has become significant in recent years. With each new technology node this variability is becoming more prominent. In this work, we present a general Statistical Timing Analysis (STA) framework that captures spa ..."
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Cited by 38 (6 self)
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The impact of parameter variations on timing due to process and environmental variations has become significant in recent years. With each new technology node this variability is becoming more prominent. In this work, we present a general Statistical Timing Analysis (STA) framework that captures spatial correlations between gate delays. Our technique does not make any assumption about the distributions of the parameter variations, gate delay and arrival times. We propose a Taylorseries expansion based polynomial representation of gate delays and arrival times which is able to e#ectively capture the nonlinear dependencies that arise due to increasing parameter variations. In order to reduce the computational complexity introduced due to polynomial modeling during STA, we propose an e#cient linearmodeling driven polynomial STA scheme. On an average the degree2 polynomial scheme had a 7.3x speedup as compared to Monte Carlo with 0.049 units of rms error w.r.t Monte Carlo. Our technique is generic and can be applied to arbitrary variations in the underlying parameters.
Statistical Timing Analysis with Correlated NonGaussian Parameters using Independent Component Analysis
 In ACM/IEEE International Workshop on Timing Issues
, 2006
"... We propose a scalable and efficient parameterized blockbased statistical static timing analysis algorithm incorporating both Gaussian and nonGaussian parameter distributions, capturing spatial correlations using a gridbased model. As a preprocessing step, we employ independent component analysis ..."
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Cited by 32 (3 self)
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We propose a scalable and efficient parameterized blockbased statistical static timing analysis algorithm incorporating both Gaussian and nonGaussian parameter distributions, capturing spatial correlations using a gridbased model. As a preprocessing step, we employ independent component analysis to transform the set of correlated nonGaussian parameters to a basis set of parameters that are statistically independent, and principal components analysis to orthogonalize the Gaussian parameters. The procedure requires minimal input information: given the moments of the variational parameters, we use a Padé approximationbased moment matching scheme to generate the distributions of the random variables representing the signal arrival times, and preserve correlation information by propagating arrival times in a canonical form. For the ISCAS89 benchmark circuits, as compared to Monte Carlo simulations, we obtain average errors of 0.99 % and 2.05%, respectively, in the mean and standard deviation of the circuit delay. For a circuit with G  gates and a layout with g spatial correlation grids, the complexity of our approach is O(gG).
Defining statistical sensitivity for timing optimization of logic circuits with largescale process and environmental variations,” Docket MC06172004P, Filed with the US Patent Office
, 2005
"... The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how o ..."
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Cited by 21 (3 self)
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The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper [1] we demonstrate why the traditional concepts of slack and critical path become ineffective under largescale variations, and we propose a novel sensitivitybased metric to assess the “criticality ” of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples. 1.
Statistical timing analysis using levelized covariance propagation
 in Proc. DATE, 2005
"... Variability in process parameters is making accurate timing analysis of nanoscale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for statistical timing analysis using Levelized Covariance Propagation (LCP). The algorithm simultaneously considers the i ..."
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Cited by 16 (4 self)
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Variability in process parameters is making accurate timing analysis of nanoscale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for statistical timing analysis using Levelized Covariance Propagation (LCP). The algorithm simultaneously considers the impact of random placement of dopants (which makes every transistor in a die independent in terms of threshold voltage) and the spatial correlation of the process parameters such as channel length, transistor width and oxide thickness due to the intradie variations. It also considers the signal correlation due to reconvergent paths in the circuit. Results on several benchmark circuits in 70nm technology show an average of 0.21 % and 1.07 % errors in mean and the standard deviation, respectively, in timing analysis using the proposed technique compared to the MonteCarlo analysis. 1.
Synthesizing a Representative Critical Path for PostSilicon Delay Prediction
"... Several approaches to postsilicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit after manufacturing. For realistic circuits, where the number of critical paths can be large, the notion of using a single ..."
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Cited by 13 (3 self)
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Several approaches to postsilicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit after manufacturing. For realistic circuits, where the number of critical paths can be large, the notion of using a single critical path is too simplistic. This paper overcomes this problem by introducing the idea of synthesizing a representative critical path (RCP), which captures these complexities of the variations. We first prove that the requirement on the RCP is that it should be highly correlated with the circuit delay. Next, we present two novel algorithms to automatically build the RCP. Our experimental results demonstrate that over a number of samples of manufactured circuits, the delay of the RCP captures the worst case delay of the manufactured circuit. The average prediction error of all circuits is shown to be below 2.8 % for both approaches. For both our approach and the critical path replica method, it is essential to guardband the prediction to ensure pessimism: our approach requires a guard band 30 % smaller than for the critical path replica method.
An accurate sparse matrix based framework for statistical static timing analysis
 in ICCAD ’06: Proceedings of the 2006 IEEE/ACM International conference on Computeraided design
, 2006
"... Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such ..."
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Cited by 12 (2 self)
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Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparsematrix based framework for accurate pathbased SSTA, motivated by the observation that the number of timing paths in practice is subquadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparsematrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomialbased delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising. 1.
NonGaussian Statistical Parameter Modeling for SSTA with Confidence Interval Analysis
"... Abstract — Most of the existing statistical static timing analysis (SSTA) algorithms assume that the process parameters of have been given with 100 % confidence level or zero errors and are preferable Gaussian distributions. These assumptions are actually quite questionable and require careful atten ..."
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Cited by 7 (1 self)
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Abstract — Most of the existing statistical static timing analysis (SSTA) algorithms assume that the process parameters of have been given with 100 % confidence level or zero errors and are preferable Gaussian distributions. These assumptions are actually quite questionable and require careful attention. In this paper, we aim at providing solid statistical analysis methods to analyze the measurement data on testing chips and extract the statistical distribution, either Gaussian or nonGaussian which could be used in advanced SSTA algorithms for confidence interval or error bound information. Two contributions are achieved by this paper. First, we develop a moment matching based quadratic function modeling method to fit the first three moments of given measurement data in plain form which may not follow Gaussian distributions. Second, we provide a systematic way to analyze the confident intervals on our modeling strategies. The confidence intervals analysis gives the solid guidelines for testing chip data collections. Extensive experimental results demonstrate the accuracy of our algorithm. I.
A Gate Delay Model Focusing on Current Fluctuation over WideRange of Process and Environmental Variability
"... This paper proposes a gate delay model that is suitable for timing analysis considering widerange process and environmental variability. The proposed model focuses on current variation and its impact on delay is considered by replacing output load. The proposed model is applicable for large variabi ..."
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Cited by 7 (2 self)
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This paper proposes a gate delay model that is suitable for timing analysis considering widerange process and environmental variability. The proposed model focuses on current variation and its impact on delay is considered by replacing output load. The proposed model is applicable for large variability with current model constructed by DC analysis whose cost is small. The proposed model can also be used both in statistical static timing analysis and in conventional cornerbased static timing analysis. Experimental results in a 90nm technology show that the gate delays of inverter, NAND and NOR are accurately estimated under gate length, threshold voltage, supply voltage and temperature fluctuation. We also verify that the proposed model can cope with slow input transition and RC output load. We demonstrate applicability to multiplestage path delay and flipflop delay, and show an application of sensitivity calculation for statistical timing analysis.
Convergenceprovable statistical timing analysis with levelsensitive latches and feedback loops
 in Proc. ASPDAC
, 2006
"... ABSTRACT Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing methods are either having exponential complexity or unable to treat the random variable's selfdependence caus ..."
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Cited by 6 (0 self)
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ABSTRACT Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing methods are either having exponential complexity or unable to treat the random variable's selfdependence caused by the coexistence of levelsensitive latches and feedback loops. In this paper, an efficient iterative statistical timing algorithm with provable convergence is proposed for latchbased circuits with feedback loops. Based on a new notion of iteration mean, we prove that the algorithm converges unconditionally. Moreover, we show that the converged value of iteration mean can be used to predict the circuit yield during design time. Tested by ISCAS'89 benchmark circuits, the proposed algorithm shows an error of 1.1% and speedup of 303× on average when compared with the Monte Carlo simulation.