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Peace: A hardware-software codesign environment for multimedia embedded systems. (2007)

by S Ha
Venue:ACM ToDAES
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A case study of MPEG4 decoder design with SystemBuilder,” VLSI-DAT

by Seiya Shibata , Shinya Honda , Hiroyuki Tomiyama , Hiroaki Takada , 2009
"... Abstract-This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named SystemBuilder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the be ..."
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Abstract-This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named SystemBuilder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15fps performance with pipelined hardware implementation.
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...capabilities have been increasing. Recent growth of high-level synthesis (HLS) tools has enabled hardware designers to develop hardware modules at behavioral level using C/C++ like languages [1]. By means of compilers and HLS tools, whole system can be described in a single behavioral language in short time. However, explorations of system architecture should be done properly at system-level which is higher than software/hardware-level, to obtain optimized software/hardware partitioning and communications between them. Various researches have been conducted on system-level design tools. PeaCE [2] is a system design tool featuring implementation generation from models. System modeling should be done by designers using modeling method specially designed for PeaCE. ARTS [3] provides a simulation platform for multi-processor SoCs modeled in SystemC. It supports multiple processing element (PE) models and network model among PEs. ARTS assumes that the application model simulated on it is already developed and separated properly in order to explore allocation to PEs. In industrial system design processes, however, systems are often developed from existing sequential programs by converting t...

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

by Ghislain Roquier , Endri Bezati , Marco Mattavelli
"... The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities. However, one obstacle for exploiting all the promises of such platforms is deeply rooted in sequential thinking. The sequential pro ..."
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The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities. However, one obstacle for exploiting all the promises of such platforms is deeply rooted in sequential thinking. The sequential programming model does not naturally expose potential parallelism that effectively permits to build parallel applications that can be efficiently mapped on different kind of platforms. A shift of paradigm is necessary at all levels of application development to yield portable and scalable implementations on the widest range of heterogeneous platforms. This paper presents a design flow for the hardware and software synthesis of heterogeneous systems allowing to automatically generate hardware and software components as well as appropriate interfaces, from a unique high-level description of the application, based on the dataflow paradigm, running onto heterogeneous architectures composed by reconfigurable hardware units and multicore processors. Experimental results based on the implementation of several video coding algorithms onto heterogeneous platforms are also provided to show the effectiveness of the approach both in terms of portability and scalability.
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... of MATLAB code to model applications. The HW back-end (Laura) then turns the KPN model expressed by MATLAB code to VHDL. KPN-based models are much more expressive than more restricted MoC and can cover a much broader class of applications. However, since analyzability is, roughly speaking, inversely related to the expressiveness, it is somehow difficult to figure out the ability to generate the corresponding KPN models of more complex applications written in MATLAB. PeaCE from the Seoul National University is an approach that lays at midway between dataflow (synchronous dataflow—SDF) and FSM [7]. This model raises the level of expressiveness, by enabling the usage of more control structures using FSM inside SDF vertices and vice versa. However, while PeaCE generates the code for composing blocks of the model both is SW and HW, it lacks code generation support for the blocks themselves and thus requires the definition of HW-SW blocks in later stage, which is time consuming when targeting several kinds of platforms. Another interesting approach is SystemCoDesigner from the University of Erlangen-Nuremberg [8]. SystemCoDesigner is an actor-oriented approach using a high-level language n...

Modeling, Synthesis, and Validation of Heterogeneous Biomedical Embedded Systems

by Gunar Schirner
"... Abstract-The increasing performance and availability of embedded systems increases their attractiveness for biomedical applications. With advances in sensor processing and classification algorithms, real-time decision support in patient monitoring becomes feasible. However, the gap between algorith ..."
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Abstract-The increasing performance and availability of embedded systems increases their attractiveness for biomedical applications. With advances in sensor processing and classification algorithms, real-time decision support in patient monitoring becomes feasible. However, the gap between algorithm design and their embedded realization is growing. This paper overviews an approach for development of biomedical devices at an abstract algorithm level with automatic generation of an embedded implementation. Based on a case study of a Brain Computer Interface (BCI), this paper demonstrates capturing, modeling and synthesis of such applications.
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...ion. These languages are based on common programming languages C++ and C, which eases the acceptance for software developers. After successfully capturing a design at the high level, the next major task is the design space exploration to explore suitable platform candidates considering trade-offs between hardware and software implementations. ESL Synthesis Methodologies (see overview in [8]) are emerging that systematically refine a system specification toward a platform implementation. Examples include Dedalus [9], SCE [10], SystemCoDesigner [11], Metropolis [12], Koski [13], and PeaCE/HOPES [14]. These methodologies use the concept of virtual platforms (VPs) for a functional performance simulation of real platforms (consisting of processors, hardware accelerators, memories, and bus hierarchies). In this paper, we harness the power of the ESL environment System-on-Chip (SCE) [10] for exploring design alternatives and generating an embedded implementation for biomedical applications focusing on body brain interface systems. III. APPROACH A. Overview The overall design flow is highlighted in Fig. 1. At its input, the user specifies the application as a set of algorithms, basically in fo...

A predictable multiprocessor desgin flow for streaming applications with dynamic behaviour A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour

by Sander Stuijk , Marc Geilen , Twan Basten
"... Abstract-The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable design flow is needed. The result should be a system that guarantees that an application can perform its own tasks w ..."
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Abstract-The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable design flow is needed. The result should be a system that guarantees that an application can perform its own tasks within strict timing deadlines, independent of other applications running on the system. Synchronous Dataflow Graphs (SDFGs) provide predictability and are often used to model time-constrained streaming applications that are mapped onto a multiprocessor platform. However, the model abstracts from the dynamic application behaviour which may lead to a large overestimation of its resource requirements. We present a design flow that takes the dynamic behaviour of applications into account when mapping them onto a multiprocessor platform. The design flow provides throughput guarantees for each application independent of the other applications while taking into account the available processing capacity, memory and communication bandwidth. The design flow generates a set of mappings that provide a trade-off in their resource usage. This trade-off can be used by a run-time mechanism to adapt the mapping in different use-cases to the available resource. The experimental results show that our design flow reduces the resource requirements of an MPEG-4 decoder by 66% compared to a state-of-the-art design flow based on SDFGs.
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...o map multiple applications onto a multiprocessor platform with the objective to minimize resource usage while meeting a throughput constraint. These flows assume that each application is modeled with a Cyclo-Static Dataflow Graph ([15]), or an SDFG ([2], [20]), or a homogeneous SDFG ([12]). These models abstract from (most of) the dynamic behaviour of an application. This may lead to a large overestimation of the resource requirements of the application. Our application model and design flow are able to capture and exploit the dynamic behaviour when allocating resources. The design flow from [7] can deal with applications that exhibit a dynamic behaviour. The design flow can however not provide timing guarantees which is needed to guarantee the robust behaviour of multimedia systems. All aforementioned work only considers the binding and scheduling of an application onto a multiprocessor platform, VLD IDCT RCMCFD x xx x = {0, 30, 40, 50, 60, 70, 80, 99} Figure 1. Scenario graph of an MPEG-4 SP decoder. our flow considers also these steps, but it also considers the dimensioning of the buffers between the tasks of an application. These buffers have a large impact on the throughput of t...

Joint Algorithm Developing and System-Level Design: Case Study on Video Encoding

by Jiaxing Zhang , Gunar Schirner
"... Abstract. System-Level Design Environments (SLDEs) are often utilized for tackling the design complexity of modern embedded systems. SLDEs typically start with a specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little o ..."
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Abstract. System-Level Design Environments (SLDEs) are often utilized for tackling the design complexity of modern embedded systems. SLDEs typically start with a specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little or no hardware concern. Currently, algorithm and system design environments are disjoint; system level specifications are manually implemented which leads to the specification gap. In this paper, we bridge algorithm and system design environments creating a unified design flow facilitating algorithm and system co-design. It enables algorithm realizations over heterogeneous platforms, while still tuning the algorithm according to platform needs. Our design flow starts with algorithm design in Simulink, out of which a System Level Design Language (SLDL)-based specification is synthesized. This specification then is used for design space exploration across heterogeneous target platforms and abstraction levels, and, after identifying a suitable platform, synthesized to HW/SW implementations. It realizes a unified development cycle across algorithm modeling and system-level design with quick responses to design decisions on algorithm-, specification-and system exploration level. It empowers the designer to combine analysis results across environments, apply cross layer optimizations, which will yield an overall optimized design through rapid design iterations. We demonstrate the benefits on a MJPEG video encoder case study, showing early computation/communication estimation and rapid prototyping from Simulink models. Results from Virtual Platform performance analysis enable the algorithm designer to improve model structure to better match the heterogeneous platform in an efficient and fast design cycle. Through applying our unified design flow, an improved HW/SW is found yielding 50% performance gain compared to a pure software solution.
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...ts with diverse and distinct architecture characteristics heterogeneously to achieve efficient and flexible platform solutions, which however, dramatically increases design complexity. G. Schirner et al. (Eds.): IESS 2013, IFIP AICT 403, pp. 26–38, 2013. c© IFIP International Federation for Information Processing 2013 Joint Algorithm Developing and System-Level Design 27 In order to tame the complexity, System-Level Design (SLD) has emerged with methodologies, tools and environments for a systematic design at higher levels of abstraction. System-Level Design Environments (SLDE), such as PeaCE [5] and SoC Environment (SCE) [2] operate on an input specification captured in an System-Level Design Language (SLDL), such as SystemC[15] and SpecC[3]. Based on an input specification, SLDEs provide design space exploration through early performance estimation, automated refinement into Transaction Level Models (TLM), and detailed analysis capabilities. Designers can use their synthesis to generate target implementations. A typical SLD environment is shown at the lower half of Fig. 1. System-Level Design Env. Refinements Specification Synthesis TLM/PAM A nalysis Algorithm Development Env. Model...

[ Hae-woo Park, Hyunok Oh, and Soonhoi Ha] Multiprocessor SoC Design Methods and Tools

by unknown authors
"... [Software development on multicore platforms] With the continuous evolution of semiconductor process technology, it is now possible to integrate tens or hundreds of processors in a single chip and make an multiprocessor systems-on-chip (MPSoC), or a multicore platform. There are many dual or quad-co ..."
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[Software development on multicore platforms] With the continuous evolution of semiconductor process technology, it is now possible to integrate tens or hundreds of processors in a single chip and make an multiprocessor systems-on-chip (MPSoC), or a multicore platform. There are many dual or quad-core CPUs and 1001-core graphics processing units (GPUs) on the desktop computer market, and many MPSoC solutions are also in the embedded computing markets. A key benefit of multicore platforms is scalability in performance and power. On the other hand, signal processing applications
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... UIUC MATLAB, C11 HTA DATA-TYPE & OPERATIONS NO ASSUMPTION IEEE SIGNAL PROCESSING MAGAZINE [75] NOVEMBER 2009proposes a novel meta-model that can be refined to a specific model of computation. PeaCE =-=[19]-=- is a hardware-software codesign environment that uses three models of computation with predefined rules of usage. In an actor-based model, an application task is specified as a set of actors, or modu...

Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based

by Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich
"... Abstract. System-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic subtasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have be ..."
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Abstract. System-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic subtasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have been proposed. However, it was shown that each of these approaches has drawbacks in at least one of the four subtasks. In this paper, we present our efforts towards a comprehensive system-level synthesis by combining two academic system-level solutions into a seamless approach that automatically explores and generates pinaccurate implementation-level models starting from a formal application model and a generic MPSoC platform. We analyze the system-level synthesis flow and define intermediate representations in terms of transaction level models that serve as link between existing tools; automated transformations between these models are presented. Furthermore, we drive design decisions for both flows through a single design space exploration engine. We demonstrate the resultant flow and show the benefits of fully automatic exploration and synthesis for rapid and early systemlevel design. 1
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...ion of different ESL synthesis approaches [10] with updates Decision Making Refinement Approach DSE Comp. Comm. Comp. Comm. Daedalus [28] • • ◦ • ◦ Koski [27] • • ◦ • ◦ Metropolis [1] – ◦ – ◦ – PeaCE =-=[14, 18]-=- • ◦ ◦ • ◦ SCE [6] – – – • • SystemCoDesigner [16] • • • • – – no support ◦ partial support • full support separation of decision making and refinement, both steps are typically performed separately f...

Realizing Software Defined Radio -- A Study in Designing Mobile Supercomputers

by Yuan Lin , 2008
"... The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform cap ..."
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The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or Software Defined Radio (SDR), has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this under the power budget of a mobile device. Wireless communications belong to an emerging class of applications with the processing requirements of a supercomputer but the power constraints of a mobile device – mobile supercomputing. This thesis presents a set of design proposals for building a programmable wireless communication solution. In order to design a solution that can meet the lofty requirements of SDR, this thesis takes an application-centric design approach – evaluate andoptimize all aspects of the design based on the characteristics of wireless communication protocols. This includes a DSP processor architecture optimized for wireless baseband processing,
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...Some of these are frameworks that are designed for a wide range of application by supporting multiple dataflow models, such as the Ptolemy project [49], the DIF format [42], and the PeaCE design flow =-=[36]-=-. There also have been languages that are designed explicitly for a processor architecture. StreamIt [79] was proposed for mapping streaming computations onto tiled processor architectures. The origin...

A Timed HW/SW Coemulation Technique for Fast Yet Accurate System Verification

by Hoeseok Yang, Youngmin Yi, Soonhoi Ha
"... Abstract — In System-on-chip (SoC) design, it is essential to verify the correctness of design before a chip is fabricated. While conventional hardware emulators validate functional correctness of hardware components quickly, only a few researches exist to use hardware emulators for timing verificat ..."
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Abstract — In System-on-chip (SoC) design, it is essential to verify the correctness of design before a chip is fabricated. While conventional hardware emulators validate functional correctness of hardware components quickly, only a few researches exist to use hardware emulators for timing verification since synchronization between the hardware emulator and the other parts easily overwhelms the gain of hardware emulator. In this paper we propose a novel hardware/software coemulation framework for fast yet accurate system verification based on the virtual synchronization technique. For virtual synchronization, interface protocol and interface logic between a hardware emulator and the HW/SW coemulation kernel are proposed. Experiments with real-life examples prove the effectiveness of the proposed technique. Keywords- coemulation; cosimulation; synchronization; verification; I.
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...ardware Interface Module The HW IF module models the bus interface and synchronization logic of the target architecture as shown in Figure 4. In the model-based hardware/software codesign environment =-=[15]-=-, the hardware interface logic is automatically synthesized. Figure 6 shows an example case where the hardware block has two input ports and one output ports: A receiver(RCV)/sender(SND) interface is ...

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...to the bridge module in order to raise the level of abstraction. The bridge is described and compiled using a bridge specification language (BSL). Another framework is PeaCE which is based on Ptolemy =-=[11]-=-, [20]. It also provides the possibility to connect external tools to the design flow. The limitation to that approach is that it is bound to use Ptolemy as a central element. A framework for software...

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