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Physically justifiable dielevel modeling of spatial variation in view of systematic across wafer variability
 in Proc. Design Autom. Conf
, 2009
"... Abstract—Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic acrosswafer varia ..."
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Abstract—Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic acrosswafer variation, and purely random spatial variation is not significant. We analytically study the impact of acrosswafer variation and show how it gives an appearance of correlation. We have developed a new dielevel variation model considering deterministic acrosswafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable. Experimental results show that for statistical timing and leakage analysis, our model is within 2% and 5 % error from exact simulation result, respectively, while the error of the existing distancebased spatial variation model is up to 6.5 % and 17%, respectively. Moreover, our new model is also 6 × faster than the spatial variation model for statistical timing analysis and 7 × faster for statistical leakage analysis. Index Terms—Leakage analysis, spatial correlation, SSTA, timing analysis, yield modeling.
Ant Colony Optimization for Power Efficient Routing in Manhattan and NonManhattan VLSI Architectures
"... increased the number of transistors that fit on a single chip to about two billion. In such complex designs, a primary design goal is to limit the power consumption of the chip. Power consumption depends on capacitance, which depends on the length of wires on the chip and the number of vias which co ..."
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increased the number of transistors that fit on a single chip to about two billion. In such complex designs, a primary design goal is to limit the power consumption of the chip. Power consumption depends on capacitance, which depends on the length of wires on the chip and the number of vias which connect wires on different layers of the chip. We use Ant Colony Optimization (ACO) algorithms to minimize wirelength, vias and capacitance. ACO provide a multiagent framework for combinatorial optimization by combining memory, stochastic decision making and strategies of collective and distributed learning by antlike agents. This paper applies ACO to the NPhard problem of finding optimal routes with minimum capacitance for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We implemented ACO algorithms on both manhattan and nonmanhattan routing architectures. The results are compared with several state of the art academic routers. The ACO routing algorithm was able to obtain an overall improvement of 9 % in terms of wirelength, 7 % in terms of vias and 18 % in terms of capacitance. Running times were longer than those routers, but very similar to the other router which is able to route all wires on all benchmark chips. I.
An Enhanced CongestionDriven Floorplanner
"... Abstract: In this paper, a rectilinearbased congestiondriven floorplanning algorithm is presented to enhance the wire congestion and the CPU runtime. The proposed algorithm contains two stages, including the simulatedannealing (SA) based approach with the concept of ant algorithm (SANTA) and the ..."
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Abstract: In this paper, a rectilinearbased congestiondriven floorplanning algorithm is presented to enhance the wire congestion and the CPU runtime. The proposed algorithm contains two stages, including the simulatedannealing (SA) based approach with the concept of ant algorithm (SANTA) and the nonlinear programming based method. The objective of the first stage and the second stage are to minimize the multiple objectives, such as the area, wire length and wire congestion, and to further improve the wire congestion of the local congested region without the area overhead, respectively. First, the effective concept of the ant algorithm is integrated into the multiple objectives floorplanner, which simultaneously minimizes area, wire congestion and the total wire length, to speedup the runtime. Besides, the nonlinear programming (NLP) based formulations are provided to perform the module reshaping, which maximizes the common length between two adjacent congested modules. For the floorplanner, the sequentialpair (SP) presentation is utilized to deal with the floorplan data at every iteration. For each iteration of the floorplanner, we first use SANTA to improve the neighbor searching and reduce the runtime. After performing the first state, we will obtain a floorplan with the objectives of the area, wire congestion and total length. For the intermediate floorplan, we select the two adjacent soft modules located at the most congested regions and divide the two soft modules into a set of connected subrectangles. Hence, we further reduce the congestion by enlarging the common boundary between