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50
A CMOS switched transconductor mixer
- IEEE Journal of Solid-State Circuits
"... Abstract—A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-cou ..."
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Cited by 14 (2 self)
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Abstract—A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18- m CMOS to operate at only a 1-V supply. Experimental re-sults show satisfactory mixer performance up to 4 GHz and con-firm the fundamental noise benefit. Index Terms—Active circuits, active mixers, CMOS analog integrated circuits, communication circuits, demodulation, dielec-tric breakdown, down-conversion mixers, frequency conversion, integrated circuit noise, intermodulation distortion, linear trans-conductance, low-noise design, low-voltage, microwave integrated circuits, microwave mixers, modulation, noise, nonlinear circuits, receiver, reliability, transmitter, white noise, 1 noise. I.
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Cited by 6 (2 self)
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The quality d thi. npmnidion i. ôopmdmt upm th. q d ü y of the copy submitbû. Brolren or indistinct prïnt, cokred or par quaI'i iliustmtions and photogmphs, print ~ f w g h, uibstandard margins, nd impfqmr alignrnent can adverse(y dbct mproductiorr. In the unlikely event that the author did not smd UMI a complets tvm"i~sCtipt and there are missing pages, ümse Wl be m. Also, if unautnomed copyright material had to be removeâ, a note will i n d m the deletion. Oversize materials (8.9..-S. drawings, cherb) are mpmduced by sectiming the original, bsginning at the upper left-hanâ amer anâ contiming from left to right in equal sections with small wedags. Photographs induded in the original manuscript have bieeri teproduoed xemgraphically in mis copy. HigW guality 6m x 9 " b k k anâ W i photographie prints are avaihûîe for any Qhotogriap)rs or illustratims apoearing in this copy for an additionol charge. Contas UMI di * to order-Ml & H-l Inhmatbn and Lmrning
Characterization of IIP2 and DC-Offsets in Transconductance Mixers
- IEEE Trans. Circuits Syst. II
, 2001
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2.4/5.7-GHz CMOS dual-band low-IF architecture using Weaver-Hartley image-rejection techniques
- IEEE Trans. Microw. Theory Tech
, 2009
"... ture, using 0.18- m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demon-strated architecture rejects not only the fi ..."
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Cited by 4 (1 self)
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ture, using 0.18- m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demon-strated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explana-tion is employed to obtain the image-rejection mechanisms of the Weaver–Hartley architecture. Index Terms—Divider, Hartley architecture, image rejection, secondary image rejection, Weaver architecture.
A Design System for RFIC: Challenges and Solutions
- Proc. of the IEEE
, 2000
"... The expansion of the market for portable wireless communication devices has given a tremendous push to the development of a new generation of low-power radio frequency integrated circuit (RFIC) products. In this fast-growing environment where time-to-market constraints force tight schedules, having ..."
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Cited by 3 (0 self)
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The expansion of the market for portable wireless communication devices has given a tremendous push to the development of a new generation of low-power radio frequency integrated circuit (RFIC) products. In this fast-growing environment where time-to-market constraints force tight schedules, having a good design methodology, innovative computer-aided design (CAD) tools, and a well-integrated design system are key factors to success. In this paper, we describe a design system developed to provide the designer with everything necessary to accurately predict the behavior of RFIC devices, including layout and package parasitic effects. We show how important a well-defined and integrated system is to manufacturing a design that meets specifications at the minimum cost, in the minimum time. A close link between schematic, models, and layout is of paramount importance to ensure the accuracy needed for low-power RF design. We give an overview of the advanced methods and tools currently available for simulation and noise analysis of RF devices. Finally, we show a design example that obtained first-silicon success. Keywords—Design automation, design methodology, design system, device modeling, layout design, layout parasitics, low power, power amplifier, RF integrated circuit design, RF integrated circuit simulation, substrate coupling, substrate noise. I.
A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion Receivers
"... Abstract- This paper presents an integrated quadrature demodulator with on-chip frequency divider implemented in a 0.13 µm CMOS technology. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture ..."
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Abstract- This paper presents an integrated quadrature demodulator with on-chip frequency divider implemented in a 0.13 µm CMOS technology. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. From 700MHz to 2.5GHz, the demodulator achieves 10dB DSB NF with 9-33 kHz 1/f-noise corner and 35dB of low frequency voltage gain. The total chip draws 20mA-24mA from a single 1.5V supply. I.
GaInP/GaAs HBT sub-harmonic Gilbert mixers using stacked-LO and leveled-LO topologies
- IEEE Trans Microwave Theory Tech
"... Abstract—This paper discusses and demonstrates the most popular sub-harmonic Gilbert mixers in 2- m GaInP/GaAs HBT technology. High two local oscillators (2LO)-to-RF isolation is important to alleviate the self-mixing problem of the sub-har-monic mixer. The demonstrated GaInP/GaAs HBT stacked-local ..."
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Abstract—This paper discusses and demonstrates the most popular sub-harmonic Gilbert mixers in 2- m GaInP/GaAs HBT technology. High two local oscillators (2LO)-to-RF isolation is important to alleviate the self-mixing problem of the sub-har-monic mixer. The demonstrated GaInP/GaAs HBT stacked-local oscillator (LO) mixer topology has achieved the best 2LO-to-RF isolation when compared with the previous literature. On the other hand, the leveled-LO sub-harmonic mixers have advantages in terms of the high speed and low dc supply voltage at the cost of much larger LO pumping power. Among all the structures, the bottom-LO sub-harmonic mixer has the lowest current con-sumption and the simplest circuit structure at the expense of the 2LO-to-RF isolation. Index Terms—DC offset, GaInP/GaAs HBT, Gilbert mixer, self-mixing, sub-harmonic mixer, two local oscillators (2LO)-to-RF iso-lation. I.
Phase noise in LC oscillators: A phasor-based analysis of a general result and of loaded Q
- IEEE transactions on Circuits and systems
, 2010
"... has offered a general result concerning phase noise in nearly-si-nusoidal inductance–capacitance (LC) oscillators; namely that the noise factor of such oscillators (under certain achievable condi-tions) is largely independent of the specific operation of individual transistors in the active circuitr ..."
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Cited by 2 (0 self)
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has offered a general result concerning phase noise in nearly-si-nusoidal inductance–capacitance (LC) oscillators; namely that the noise factor of such oscillators (under certain achievable condi-tions) is largely independent of the specific operation of individual transistors in the active circuitry. Both use the impulse sensitivity function (ISF). In this work, we show how the same result can be obtained by generalizing the phasor-based analysis. Indeed, as ap-plied to nearly-sinusoidal LC oscillators, we show how the two ap-proaches are equivalent. We analyze the negative-gm LC model and present a simple equation that quantifies output noise resulting from phase fluctuations. We also derive an expression for output noise resulting from amplitude fluctuations. Further, we extend the analysis to consider the voltage-biased LC oscillator and fully dif-ferential CMOS LC oscillator, for which the Bank’s general result does not apply. Thus we quantify the concept of loaded. Index Terms—Impulse sensitivity function, noise factor, oscilla-tors, voltage controlled oscillator, phase noise. I.
Tradeoffs and Design of an Ultra Low Power UHF Transceiver Integrated
- in a Standard Digital CMOS Process,” Proceedings of the 2000 International Symposium on Low power electronics and design
, 2000
"... A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between per ..."
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A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5m digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1mW in receive mode. It achieves a-95dBm sensitivity for a data rate of 24kbit/s. The transmitter section is designed for 0dBm output power under the minimum 1V supply, with a global efficiency higher than 15%.
A high performance CMOS direct down conversion mixer for UWB system
- IErCE Trans. Electron
, 2005
"... This paper represents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra ind ..."
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Cited by 1 (0 self)
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This paper represents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.
