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Efficient reconfigurable design for pricing Asian options
 SIGARCH Comput. Archit. News
"... Arithmetic Asian options are financial derivatives which have the feature of pathdependency: they depend on the entire price path of the underlying asset, rather than just the instantaneous price. This pathdependency makes them difficult to price, as only computationally intensive MonteCarlo meth ..."
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Arithmetic Asian options are financial derivatives which have the feature of pathdependency: they depend on the entire price path of the underlying asset, rather than just the instantaneous price. This pathdependency makes them difficult to price, as only computationally intensive MonteCarlo methods can provide accurate prices. This paper proposes an FPGAaccelerated Asian option pricing solution, using a highlyoptimised parallel MonteCarlo architecture. The proposed pipelined design is described parametrically, facilitating its reuse for different technologies. An implementation of this architecture in a Virtex5 xc5vlx330t FPGA at 200MHz is 313 times faster than a multithreaded software implementation running on a Intel Xeon E5420 quadcore CPU at 2.5GHz; it is also 2.2 times faster than the Tesla
On comparing financial option price solvers on fpga
 in FieldProgrammable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on
, 2011
"... AbstractA number of different numerical methods for accelerating financial option pricing using FPGAs have recently been investigated, such as MonteCarlo, finitedifference, quadrature, and binomial trees. However, these papers only compare acceleration of each method against the same method in s ..."
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AbstractA number of different numerical methods for accelerating financial option pricing using FPGAs have recently been investigated, such as MonteCarlo, finitedifference, quadrature, and binomial trees. However, these papers only compare acceleration of each method against the same method in software, and do not consider a more important practical question, which is to identify the method that provides the best FPGA performance for a given option pricing application, regardless of raw speedup over software. This paper proposes a framework for comparing the performance of numerical option pricing methods using FPGAs, taking into account both speed (time to solution) and accuracy (quality of solution), and examines how the speedaccuracy tradeoff curve varies for each method. We apply the framework to European and American option pricing problems using Virtex4 parts, and show that the quadrature solver converges fastest for both European and American options, and is also the most accurate in terms of root mean squared error for European options. However, when very accurate American results are needed the finitedifference solver is the most efficient method. Our results also show that the MonteCarlo solver is at least 100 times less accurate in log scale than those based on other pricing methodologies; this drawback outweighs its benefit of having large raw speedups found in previous papers.
Option pricing with multidimensional quadrature architectures
 in Proceedings of the 2009 International Conference on FieldProgrammable Technology, IEEE Computer Society, 2009
"... Abstract—Quadrature based methods for numerical integration provide a means of quickly and accurately pricing financial products such as options. These methods can be applied to multidimensional products, such as options on multiple underlying assets, but suffer from an exponential increase in compu ..."
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Abstract—Quadrature based methods for numerical integration provide a means of quickly and accurately pricing financial products such as options. These methods can be applied to multidimensional products, such as options on multiple underlying assets, but suffer from an exponential increase in computational complexity as the dimension increases. This paper examines the theoretical complexity of quadrature methods for pricing multidimensional options, and then relates this to practical performance in contemporary hardware. An automated system for generating hardware architectures for quadrature is used to explore the performance of increasing dimensionality in FPGA implementations, and then compared them to GPU and CPU solutions. We find that a singleprecision FPGA can provide 25 times speedup over software in three dimensions, and offers slightly improved performance over a GPU using comparable technology. The latest GPUs are 2.7 times faster than the older technology Virtex4 FPGA, but the FPGA still provides over 9 times the energy efficiency. I.
UNIFYING FINITE DIFFERENCE OPTIONPRICING FOR HARDWARE ACCELERATION
"... Explicit finite difference method is widely used in finance for pricing many kinds of options. Its regular computational pattern makes it an ideal candidate for acceleration using reconfigurable hardware. However, because the corresponding hardware designs must be optimised both for the specific opt ..."
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Explicit finite difference method is widely used in finance for pricing many kinds of options. Its regular computational pattern makes it an ideal candidate for acceleration using reconfigurable hardware. However, because the corresponding hardware designs must be optimised both for the specific option and the target platform, it is challenging and time consuming to develop all the designs efficiently. This paper presents a framework for describing and automatically implementing financial explicit finite difference procedures in reconfigurable hardware, allowing parallelised fully pipelined implementations to be created from highlevel mathematical expressions. The proposed methodology is demonstrated using three option pricing problems. Our results show that the implementation generated by our framework on a Virtex6 device at 310MHz is more than 24 times faster than a software implementation fully optimised by the Intel compiler on a fourcore Xeron CPU at 2.66GHz. In addition, the latency of the FPGA solvers is up to 90 times lower than the corresponding software solvers. 1
Accelerating Implicit Finite Difference Schemes Using a Hardware Optimised Implementation of the Thomas
"... Abstract—The design and implementation of the Thomas algorithm optimised for hardware acceleration on an FPGA is presented. The hardware based algorithm combined with custom data flow and low level parallelism available in an FPGA reduces the overall complexity from 8N down to 5N arithmetic operatio ..."
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Abstract—The design and implementation of the Thomas algorithm optimised for hardware acceleration on an FPGA is presented. The hardware based algorithm combined with custom data flow and low level parallelism available in an FPGA reduces the overall complexity from 8N down to 5N arithmetic operations, and combined with a data streaming interface reduces memory overheads to only 2 Nlength vectors per Ntridiagonal system to be solved. The Thomas Core developed allows for multiple tridiagonal systems to be solved in parallel, giving potential use for solving multiple implicit finite difference schemes or accelerating higher dimensional alternatingdirectionimplicit schemes used in financial derivatives pricing. This paper also discusses the limitations arising from the fixedpoint arithmetic used in the design and how the resultant rounding errors can be controlled to meet a specified tolerance level. I.