Results 11  20
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35
A faster counterexample minimization algorithm based on refutation analysis
 in Design, Automation and Test in Europe, 2005
"... It is a hot research topic to eliminate irrelevant variables from counterexample, to make it easier to be understood. The BFL algorithm is the most effective counterexample minimization algorithm compared to all other approaches. But its time overhead is very large due to one call to SAT solver for ..."
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It is a hot research topic to eliminate irrelevant variables from counterexample, to make it easier to be understood. The BFL algorithm is the most effective counterexample minimization algorithm compared to all other approaches. But its time overhead is very large due to one call to SAT solver for each candidate variable to be eliminated. The key to reduce time overhead is to eliminate multiple variables simultaneously. Therefore, we propose a faster counterexample minimization algorithm based on refutation analysis in this paper. We perform refutation analysis on those UNSAT instances of BFL, to extract the set of variables that lead to UNSAT. All variables not belong to this set can be eliminated simultaneously as irrelevant variables. Thus we can eliminate multiple variables with only one call to SAT solver. Theoretical analysis and experiment result shows that, our algorithm can be 2 to 3 orders of magnitude faster than existing BFL algorithm, and with only minor lost in counterexample minimization ability. 1.
Sequential equivalence checking based on Kth invariants and circuit
 SAT solving”, Proc. HLDVT Workshop ’05
"... In this paper, we first present the concept of the kth invariant. In contrast to the traditional invariants that hold for all cycles, kth invariants guarantee to hold only after the kth cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProve ..."
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In this paper, we first present the concept of the kth invariant. In contrast to the traditional invariants that hold for all cycles, kth invariants guarantee to hold only after the kth cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProver, both of which are based on circuit SAT techniques. Jointly, BMChecker and IProver are used to compute the kth invariants, and are further integrated with a sequential SAT solver for checking sequential equivalence. Experimental results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs. I.
Improved SATbased reachability analysis with observability don’t cares
 Journal on Satisfiability, Boolean Modeling and Computation
"... The dramatic performance improvements of SAT solvers over the past decade have increased their deployment in hardware verification applications. Many problems that were previously too large and complex for SAT techniques can now be handled in an efficient manner. One such problem is reachability ana ..."
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The dramatic performance improvements of SAT solvers over the past decade have increased their deployment in hardware verification applications. Many problems that were previously too large and complex for SAT techniques can now be handled in an efficient manner. One such problem is reachability analysis, whose instances are found throughout verification applications such as unbounded model checking and trace reduction. In circuitbased reachability analysis important circuit information is often lost during the circuittoSAT translation process. Observability Don’t Cares (ODCs) are an example of such information that can potentially help achieve better and faster results for the SAT solver. This work proposes to use the ODCs to improve the quality and performance of SATbased reachability analysis frameworks. Since ODCs represent variables whose values do not affect the outcome of a problem, it is possible to satisfy a problem with fewer assigned variables. This in turn leads to more compact solutions and thus fewer solutions to cover the entire solution space. Specifically, this work presents an efficient way to identify ODCs, proves the correctness of leaving ODC variables unassigned, and develops a reachability analysis platform that benefits greatly from the ODCs. The advantages of using ODCs in reachability analysis is demonstrated through extensive experiments on unbounded model checking and trace reduction applications. Keywords: SAT solver, reachability analysis, model checking, observability don’t cares
Interpolant Learning and Reuse in SATBased Model Checking
"... Bounded Model Checking (BMC) is one of the most paradigmatic practical applications of Boolean Satisfiability (SAT). The utilization of SAT in model checking has allowed significant performance gains and, as a consequence, a large number of commercial verification tools now include SATbased model c ..."
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Bounded Model Checking (BMC) is one of the most paradigmatic practical applications of Boolean Satisfiability (SAT). The utilization of SAT in model checking has allowed significant performance gains and, as a consequence, a large number of commercial verification tools now include SATbased model checkers. Recent work has provided SATbased BMC with completeness conditions, and this is generally referred to as unbounded model checking (UMC). Among the existing approaches for SATbased UMC, the utilization of interpolants is among the most effective. Despite their success, interpolants have only been used for identifying a fixed point of the set of reachable states. This paper extends the utilization of interpolants in SATbased model checking. This is achieved by observing that, under reasonable assumptions, interpolants can be reused, i.e. computed interpolants can be reused at later stages of the model checking process. The paper develops conditions for validity of interpolant reuse. In addition, the paper outlines a new fixed point condition, alternative to the existing interpolantbased fixed point condition. Preliminary practical experience on interpolant learning and reuse is reported.
Computation of Minimal Counterexamples by Using Black Box Techniques and Symbolic Methods
"... Abstract — Computing counterexamples is a crucial task for error diagnosis and debugging of sequential systems. If an implementation does not fulfill its specification, counterexamples are used to explain the error effect to the designer. In order to be understood by the designer, counterexamples sh ..."
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Abstract — Computing counterexamples is a crucial task for error diagnosis and debugging of sequential systems. If an implementation does not fulfill its specification, counterexamples are used to explain the error effect to the designer. In order to be understood by the designer, counterexamples should be simple, i.e. they should be as general as possible and assign values to a minimal number of input signals. Here we use the concept of Black Boxes — parts of the design with unknown behavior — to mask out components for counterexample computation. By doing so, the resulting counterexample will argue about a reduced number of components in the system to facilitate the task of understanding and correcting the error. We introduce the notion of ‘uniform counterexamples’ to provide an exact formalization of simplified counterexamples arguing only about components which were not masked out. Our computation of counterexamples is based on symbolic methods using AIGs (AndInverterGraphs). Experimental results using a VLIW processor as a case study clearly demonstrate our capability of providing simplified counterexamples. I.
Model checking using SMT and theory of lists
 NASA Formal Methods
, 2011
"... Abstract. A main idea underlying bounded model checking is to limit the length of the potential counterexamples, and then prove properties for the bounded version of the problem. In software model checking, that means that only program traces up to a given length are considered. Additionally, the ..."
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Abstract. A main idea underlying bounded model checking is to limit the length of the potential counterexamples, and then prove properties for the bounded version of the problem. In software model checking, that means that only program traces up to a given length are considered. Additionally, the program’s input space must be made finite by defining bounds for all input parameters. To ensure the finiteness of the program traces, these techniques typically require that all loops are explicitly unrolled some constant number of times. Here, we show how to avoid explicit loop unrolling by using the SMT Theory of Lists to model feasible, potentially unbounded program traces. We argue that this approach is easier to use, and, more importantly, increases the confidence in verification results over the typical bounded approach. To demonstrate the feasibility of this idea, we implemented a fully automated prototype software model checker and verified several example algorithms. We also applied our technique to a non software modelchecking problem from biology – we used it to analyze and synthesize correct executions from scenariobased requirements in the form of Live Sequence Charts. 1
Integrating observability don’t cares in allsolution SAT solvers
 in IEEE International Symposium on Circuits and Systems, 2006
"... Abstract — Allsolution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA industry in fields such as formal verification, circuit synthesis and automatic test pattern generation. Typically, t ..."
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Abstract — Allsolution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA industry in fields such as formal verification, circuit synthesis and automatic test pattern generation. Typically, these engines iteratively find each solution by calling a standard SAT solving procedure. Each solution is minimized using different postprocessing techniques and the problem is constrained to prevent recurring solutions. In this work, instead of applying postprocessing techniques, the objective is to minimize the size of the solution “on the fly ” during the allsolution SAT solving process. This is achieved by allowing the solver to exploit the structural circuit Observability Don’t Cares (ODC) arising from the problem. The solver makes decisions such that the number of ODCs is maximized in each solution thus leading to an overall smaller number of iterations. Through extensive experiments, it is demonstrated that integrating ODC techniques within an allsolution SAT solver results in increased performance and more compact solutions. I.
An Outlook on Design Technologies for Future Integrated Systems
, 2009
"... The economic and social demand for ubiquitous and multifaceted electronic systems—in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies—is paving the way to a new class of heterogeneous integrated systems, with increased performance and ..."
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The economic and social demand for ubiquitous and multifaceted electronic systems—in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies—is paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world. This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them.
Efficient reachability checking using sequential SAT
 in Proc. Asia South Pacific Design Automation Conf
, 2004
"... Abstract – Reachability checking and Preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. In this paper, we describe how structural analysis and conflictbas ..."
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Abstract – Reachability checking and Preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. In this paper, we describe how structural analysis and conflictbased learning are combined in order to improve the efficiency of sequential search. We use conflictbased learning and illegal state learning across timeframes. We also address issues in efficiently bounding the search space in a single timeframe and across timeframes. We analyze each of these techniques experimentally and demonstrate the advantages of each technique. We compare performance against a commercial sequential ATPG engine and VIS [13] on a set of standard benchmarks. I.
Automated abstraction by incremental refinement in interpolantbased model checking
 In Proceedings of the 2008 IEEE/ACM International Conference on ComputerAided Design, ICCAD ’08
, 2008
"... Abstract—This paper addresses the field of Unbounded Model Checking (UMC) based on SAT engines, where Craig interpolants have recently gained wide acceptance as an automated abstraction technique. We start from the observation that interpolants can be quite effective on large verification instances ..."
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Abstract—This paper addresses the field of Unbounded Model Checking (UMC) based on SAT engines, where Craig interpolants have recently gained wide acceptance as an automated abstraction technique. We start from the observation that interpolants can be quite effective on large verification instances. As they operate on SATgenerated refutation proofs, interpolants are very good at automatically abstract facts that are not significant for proofs. In this work, we push forward the new idea of generating abstractions without resorting to SAT proofs, and to accept (reject) abstractions whenever they (do not) fulfill given adequacy constraints. We propose an integrated approach smoothly combining the capabilities of interpolation with abstraction and overapproximation techniques, that do not directly derive from SAT refutation proofs. The driving idea of this combination is to incrementally generate, by refinement, an abstract (overapproximate) image, built up from equivalences, implications, ternary and localization abstraction, then (eventually) from SAT refutation proofs. Experimental results, derived from the verification of hard problems, show the robustness of our approach. I.