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An Industrially Effective Environment for Formal Hardware Verification
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
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Symbolic model checking for asynchronous boolean programs
 in SPIN
, 2005
"... Abstract. Software model checking problems generally contain two different types of nondeterminism: 1) nondeterministically chosen values; 2) the choice of interleaving among threads. Most modern software model checkers can handle only one source of nondeterminism efficiently, but not both. This ..."
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Cited by 21 (7 self)
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Abstract. Software model checking problems generally contain two different types of nondeterminism: 1) nondeterministically chosen values; 2) the choice of interleaving among threads. Most modern software model checkers can handle only one source of nondeterminism efficiently, but not both. This paper describes a SATbased model checker for asynchronous Boolean programs that handles both sources effectively. We address the first type of nondeterminism with a form of symbolic execution and fixpoint detection. We address the second source of nondeterminism using a symbolic and dynamic partialorder reduction, which is implemented inside the SATsolver’s casesplitting algorithm. The preliminary experimental results show that the new algorithm outperforms the existing software model checkers on large benchmarks. 1
Existential Quantification as Incremental SAT
 In Twentythird International Conference on Computer Aided Verification, G. Gopalakrishnan and
"... Abstract. This paper presents an elegant algorithm for existential quantifier elimination using incremental SAT solving. This approach contrasts with existing techniques in that it is based solely on manipulating the SAT instance rather than requiring any reengineering of the SAT solver or needing a ..."
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Cited by 18 (7 self)
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Abstract. This paper presents an elegant algorithm for existential quantifier elimination using incremental SAT solving. This approach contrasts with existing techniques in that it is based solely on manipulating the SAT instance rather than requiring any reengineering of the SAT solver or needing an auxiliary datastructure such as a BDD. The algorithm combines model enumeration with the generation of shortest prime implicants so as to converge onto a quantifierfree formula presented in CNF. We apply the technique to a number of hardware circuits and transfer functions to demonstrate the effectiveness of the method. 1
Maximal input reduction of sequential netlists via synergistic reparameterization and localization strategies
 in CHARME
, 2005
"... Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present several fullyautomated techniques to enable maximal input reductions of sequential netlists. First, we present a novel min ..."
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Cited by 16 (8 self)
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Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present several fullyautomated techniques to enable maximal input reductions of sequential netlists. First, we present a novel mincut based localization refinement scheme for yielding a safely overapproximated netlist with minimal input count. Second, we present a novel form of reparameterization: as a traceequivalence preserving structural abstraction, which provably renders a netlist with input count at most a constant factor of register count. In contrast to prior research in reparameterization to offset input growth during symbolic simulation, we are the first to explore this technique as a structural transformation for sequential netlists, enabling its benefits to general verification flows. In particular, we detail the synergy between these inputreducing abstractions, and with other transformations such as retiming which – as with traditional localization approaches – risks substantially increasing input count as a byproduct of its register reductions. Experiments confirm that the complementary reduction strategy enabled by our techniques is necessary for iteratively reducing large problems while keeping both prooffatal design size metrics – register count and input count – within reasonable limits, ultimately enabling an efficient automated solution. 1
Memory efficient allsolutions sat solver and its application for reachability analysis
 In Proceedings of the 5th International Conference on Formal Methods in ComputerAided Design (FMCAD
, 2004
"... Abstract. This work presents a memoryefficient AllSAT engine which, given a propositional formula over sets of important and nonimportant variables, returns the set of all the assignments to the important variables, which can be extended to solutions (satisfying assignments) to the formula. The e ..."
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Cited by 14 (1 self)
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Abstract. This work presents a memoryefficient AllSAT engine which, given a propositional formula over sets of important and nonimportant variables, returns the set of all the assignments to the important variables, which can be extended to solutions (satisfying assignments) to the formula. The engine is built using elements of modern SAT solvers, including a scheme for learning conflict clauses and nonchronological backtracking. Rediscovering solutions that were already found is avoided by the search algorithm itself, rather than by adding blocking clauses. As a result, the space requirements of a solved instance do not increase when solutions are found. Finding the next solution is as efficient as finding the first one, making it possible to solve instances for which the number of solutions is larger than the size of the main memory. We show how to exploit our AllSAT engine for performing image computation and use it as a basic block in achieving full reachability which is purely SATbased (no BDDs involved). We implemented our AllSAT solver and reachability algorithm using the stateoftheart SAT solver Chaff [19] as a code base. The results show that our new scheme significantly outperforms AllSAT algorithms that use blocking clauses, as measured by the execution time, the memory requirement, and the number of steps performed by the reachability analysis. 1
Efficient symbolic simulation via dynamic scheduling, don’t caring, and case splitting
 in CHARME
, 2005
"... Abstract. Most computeraided design frameworks rely upon building BDD representations from netlist descriptions. In this paper, we present efficient algorithms for building BDDs from netlists. First, we introduce a dynamic scheduling algorithm for building BDDs for gates of the netlist, using an ef ..."
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Cited by 5 (1 self)
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Abstract. Most computeraided design frameworks rely upon building BDD representations from netlist descriptions. In this paper, we present efficient algorithms for building BDDs from netlists. First, we introduce a dynamic scheduling algorithm for building BDDs for gates of the netlist, using an efficient hybrid of depth and breadthfirst traversal, and constant propagation. Second, we introduce a dynamic algorithm for optimally leveraging constraints and invariants as don’tcares during the building of BDDs for intermediate gates. Third, we present an automated and complete case splitting approach which is triggered by resource bounds. Unlike prior work in case splitting which focused upon variable cofactoring, our approach leverages the full power of our don’tcaring solution and intelligently selects arbitrary functions to apply as constraints to maximally reduce peak BDD size while minimizing the number of cases to be explored. While these techniques may be applied to enhance the building of BDDs for arbitrary applications, we focus on their application within cyclebased symbolic simulation. Experiments confirm the effectiveness of these synergistic approaches in enabling optimal BDD building with minimal resources. 1
Synthesizing Complementary Circuits Automatically
 ICCAD'09
, 2009
"... One of the most difficult jobs in designing communication and multimedia chips, is to design and verify complex complementary circuit pair (E, E −1), in which circuit E transforms information into a format that is suitable for transmission and storage, while E’s complementary circuit E −1 recovers t ..."
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Cited by 4 (2 self)
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One of the most difficult jobs in designing communication and multimedia chips, is to design and verify complex complementary circuit pair (E, E −1), in which circuit E transforms information into a format that is suitable for transmission and storage, while E’s complementary circuit E −1 recovers this information. In order to ease this job, we propose a novel twostep approach to synthesize complementary circuit E −1 from E fully automatically. First, we assume that the circuit E satisfies parameterized complementary assumption, which means its input can be recovered from its output under some parameter setting. We check this assumption with SAT solver and find out proper values of these parameters. Second, with parameter values and the SAT instance obtained in the first step, we build the complementary circuit E −1 with an efficient satisfying assignments enumeration technique that is specially designed for circuits with lots of XOR gates. To illustrate its usefulness and efficiency, we run our algorithm on several complex encoders from industrial projects, including PCIE and 10G ethernet, and successfully generate correct complementary circuits for them.
4. TITLE AND SUBTITLE
, 2004
"... those of the author and should not be interpreted as representing the o±cial poli ..."
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those of the author and should not be interpreted as representing the o±cial poli
Experiments with SATBased Symbolic Simulation Using Reparameterization in the Abstraction Refinement Framework
, 2004
"... no. DAAD190110485. The views and conclusions contained in this document are ..."
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no. DAAD190110485. The views and conclusions contained in this document are