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22
Lazy Satisfiability Modulo Theories
 JOURNAL ON SATISFIABILITY, BOOLEAN MODELING AND COMPUTATION 3 (2007) 141Â224
, 2007
"... Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a firstorder formula with respect to some decidable firstorder theory T (SMT (T)). These problems are typically not handled adequately by standard automated theorem provers. SMT is being recognized as increasingl ..."
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Satisfiability Modulo Theories (SMT) is the problem of deciding the satisfiability of a firstorder formula with respect to some decidable firstorder theory T (SMT (T)). These problems are typically not handled adequately by standard automated theorem provers. SMT is being recognized as increasingly important due to its applications in many domains in different communities, in particular in formal verification. An amount of papers with novel and very efficient techniques for SMT has been published in the last years, and some very efficient SMT tools are now available. Typical SMT (T) problems require testing the satisfiability of formulas which are Boolean combinations of atomic propositions and atomic expressions in T, so that heavy Boolean reasoning must be efficiently combined with expressive theoryspecific reasoning. The dominating approach to SMT (T), called lazy approach, is based on the integration of a SAT solver and of a decision procedure able to handle sets of atomic constraints in T (Tsolver), handling respectively the Boolean and the theoryspecific components of reasoning. Unfortunately, neither the problem of building an efficient SMT solver, nor even that
An efficient sequential SAT solver with improved search strategies
 in Proc. Des. Autom. and Test Eur
"... A sequential SAT solver Satori [1] was recently proposed as an alternative to combinational SAT in verification applications. This paper describes the design of SeqSAT – an efficient sequential SAT solver with improved search strategies over Satori. The major improvements include (1) a new and bet ..."
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A sequential SAT solver Satori [1] was recently proposed as an alternative to combinational SAT in verification applications. This paper describes the design of SeqSAT – an efficient sequential SAT solver with improved search strategies over Satori. The major improvements include (1) a new and better heuristic for minimizing the set of assignments to state variables, (2) a new prioritybased search strategy and a flexible sequential search framework which integrates different search strategies, and (3) a decision variable selection heuristic more suitable for solving the sequential problems. We present experimental results to demonstrate that our sequential SAT solver can achieve ordersofmagnitude speedup over Satori. We plan to release the source code of SeqSAT along with this paper. I.
1 The Tiled Bitmap Forensic Analysis Algorithm
"... Abstract — Tampering of a database can be detected through the use of cryptographicallystrong hash functions. Subsequentlyapplied forensic analysis algorithms can help determine when, what, and perhaps ultimately who and why. This paper presents a novel forensic analysis algorithm, the Tiled Bitma ..."
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Abstract — Tampering of a database can be detected through the use of cryptographicallystrong hash functions. Subsequentlyapplied forensic analysis algorithms can help determine when, what, and perhaps ultimately who and why. This paper presents a novel forensic analysis algorithm, the Tiled Bitmap Algorithm, which is more efficient than prior forensic analysis algorithms. It introduces the notion of a candidate set (all possible locations of detected tampering(s)) and provides a complete characterization of the candidate set and its cardinality. An optimal algorithm for computing the candidate set is also presented. Finally, the implementation of the Tiled Bitmap Algorithm is discussed, along with a comparison to other forensic algorithms in terms of space/time complexity and cost. An example of candidate set generation and proofs of the theorems and lemmata and of algorithm correctness can be found in the appendix.
Improved SATbased reachability analysis with observability don’t cares
 Journal on Satisfiability, Boolean Modeling and Computation
"... The dramatic performance improvements of SAT solvers over the past decade have increased their deployment in hardware verification applications. Many problems that were previously too large and complex for SAT techniques can now be handled in an efficient manner. One such problem is reachability ana ..."
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The dramatic performance improvements of SAT solvers over the past decade have increased their deployment in hardware verification applications. Many problems that were previously too large and complex for SAT techniques can now be handled in an efficient manner. One such problem is reachability analysis, whose instances are found throughout verification applications such as unbounded model checking and trace reduction. In circuitbased reachability analysis important circuit information is often lost during the circuittoSAT translation process. Observability Don’t Cares (ODCs) are an example of such information that can potentially help achieve better and faster results for the SAT solver. This work proposes to use the ODCs to improve the quality and performance of SATbased reachability analysis frameworks. Since ODCs represent variables whose values do not affect the outcome of a problem, it is possible to satisfy a problem with fewer assigned variables. This in turn leads to more compact solutions and thus fewer solutions to cover the entire solution space. Specifically, this work presents an efficient way to identify ODCs, proves the correctness of leaving ODC variables unassigned, and develops a reachability analysis platform that benefits greatly from the ODCs. The advantages of using ODCs in reachability analysis is demonstrated through extensive experiments on unbounded model checking and trace reduction applications. Keywords: SAT solver, reachability analysis, model checking, observability don’t cares
Modeling Microprocessor Faults on HighLevel Decision Diagrams
"... Abstract. Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the descripti ..."
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Abstract. Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the description method and fault models. As the complexity of digital systems continues to increase, the gate level test generation methods have become obsolete. Promising approaches are highlevel methods. In this paper, a method for describing microprocessors as a special case of digital systems is explained and modeling faults with HighLevel Decision Diagrams (HLDD) is presented. HLDDs serve as a basis for a general theory of test generation for mixedlevel representations of systems, similarly as we have Boolean algebra for logiclevel. HLDDs can be used for representing systems uniformly either at logiclevel, highlevel or simultaneously at both levels. The fault model on HLDDs represents a generalization of the classical gatelevel stuckat fault model to higher levels the latter was defined for Boolean expressions whereas the former is defined for nodes in HLDDs having more general interpretation. 1.
Good Learning and Implicit Model Enumeration
"... A large number of practical applications rely on effective algorithms for propositional model enumeration and counting. Examples include knowledge compilation, model checking and hybrid solvers. Besides practical applications, the problem of counting propositional models is of key relevancy in compu ..."
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A large number of practical applications rely on effective algorithms for propositional model enumeration and counting. Examples include knowledge compilation, model checking and hybrid solvers. Besides practical applications, the problem of counting propositional models is of key relevancy in computational complexity. In recent years a number of algorithms have been proposed for propositional model enumeration. This paper surveys algorithms for model enumeration, and proposes optimizations to existing algorithms, namely through the learning and simplification of goods. Moreover, the paper also addresses open topics in model counting related with good learning. Experimental results indicate that the proposed techniques are effective for model enumeration. 1.
SATbased calculation of source code coverage for BMC
 In GI/ITG/GMMWorkshop
, 2006
"... Property checking is the method of choice to guarantee functional correctness of a design under any input assignment and in any state. But so far only few methods to evaluate the coverage achieved by a set of properties have been presented. These methods either suffer from complexity problems known ..."
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Property checking is the method of choice to guarantee functional correctness of a design under any input assignment and in any state. But so far only few methods to evaluate the coverage achieved by a set of properties have been presented. These methods either suffer from complexity problems known from CTL model checking or are incomplete themselves due to simulationbased engines. In this work we present an approach to calculate coverage information in the context of Bounded Model Checking (BMC). The components of a design that are covered by a given set of properties are calculated. The result is presented at the source code level. The approach is explained in detail and empirically evaluated. 1
Strategies for SATbased Formal Verification
, 2007
"... Verification of digital hardware designs is becoming an increasingly complex task as the designs are incorporating more functionality, becoming complex and growing larger in size. Today, verification remains a bottleneck in meeting timetomarket requirements and consumes more than 70 % of the over ..."
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Verification of digital hardware designs is becoming an increasingly complex task as the designs are incorporating more functionality, becoming complex and growing larger in size. Today, verification remains a bottleneck in meeting timetomarket requirements and consumes more than 70 % of the overall designcosts. Traditionally, verification has been done using simulationbased approaches, where a set of appropriate teststimuli is used by the designer. As the designs become more complex, however, simulationbased techniques often fail to capture cornercase errors. Furthermore, unless exhaustively tested, these approaches do not guarantee the correctness of a system with respect to its specifications. As a consequence, formal methods for design verification have been sought after. In formal verification, the conformance of a design to a given set of specifications is proven mathematically, thereby leaving no room for unexplored search spaces. Despite the exponential time/memory complexities often involved within the formal approaches, they have shown promise in capturing subtle bugs, which were missed otherwise. In this dissertation, we focus on Boolean Satisfiability (SAT) based formal verification, which has gained tremendous importance in the recent past. Importantly, SATbased approaches often alleviate the memory explosion problem, which had been a bottleneck of the traditional symbolic (Binary Decision Diagram
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"... Current algorithms for bounded model checking use SAT methods for checking satisfiability of Boolean formulae. Methods based on the validity of Quantified Boolean Formulae (QBF) allow an exponentially more succinct representation of formulae to be checked, because no “unrolling ” of the transition r ..."
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Current algorithms for bounded model checking use SAT methods for checking satisfiability of Boolean formulae. Methods based on the validity of Quantified Boolean Formulae (QBF) allow an exponentially more succinct representation of formulae to be checked, because no “unrolling ” of the transition relation is required. These methods have not been widely used, because of the lack of an efficient decision procedure for QBF. In this paper we present an algorithm for bounded model checking that uses as succinct representation of formulae as possible with QBFbased techniques. We also provide a comparison of our technique with SATbased and QBFbased ones, using a few available solvers, on reallife industrial benchmarks. 1
of Boolean functions. In contrast to Ordered Binary Decision Diagrams
"... Abstract: Free Binary Decision Diagrams (FBDDs) are a data structure for the representation ..."
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Abstract: Free Binary Decision Diagrams (FBDDs) are a data structure for the representation