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Table 21. Watchdog Timer Prescale Select
"... In PAGE 55: ...Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table21 . See characterization data for typical values at other VCC levels.... ..."
Table 1. Error types and notation for SCOP The detailed model of one execution of the redundant component, without considering the operation of the watchdog timer, is shown in Figure 2. Table 2 shows the definitions of the states.
"... In PAGE 7: ...2.1 Dependability submodel The relevant events defined on the outcomes of one execution of the SCOP component and the notations for their probabilities are as illustrated in Table1 . The assumption of no... ..."
Table 1: Error Types and Notation for RB The detailed model of one execution of the redundant component, without considering the operation of the watchdog timer, is shown in Figure 2. Table 2 shows the definitions of the states. The graph is somewhat complex, in order to represent clearly all the possible paths of execution, showing how certain executions terminate with the first phase, while others go on
1994
"... In PAGE 5: ...2. The Dependability Submodel for RB The relevant events defined on the outcomes of one execution of the RB component and the notation for their probabilities are as illustrated in Table1 . The assumption of no compensation between errors and of perfect coverage for the AT (whose errors are only caused by faults) has allowed us to reduce the event space to be considered.... ..."
Cited by 1
Table 3: Error Types and Notation for NVP The detailed model of one execution of the redundant component, without considering the operation of the watchdog timer, is shown in Figure 5. Table 4 shows the definitions of the states. The graph shows how certain executions terminate. In practice, it will later be apparent that some of the parameters describing the model have little influence on the solution.
1994
"... In PAGE 10: ...2. The Dependability Submodel for NVP The relevant events defined on the outcomes of one execution of the NVP component and the notation for their probabilities are as illustrated in Table3 . As for RB, the assumption of no compensation between errors has allowed us to reduce the event space to be considered.... ..."
Cited by 1
Table 11. Event Table for oWatchDogTimer
"... In PAGE 8: ...8 Table11 defines a function to strobe the watchdog timer when no fault has been detected. The first row states that oWatchDogTimer is set to true when it has remained false for 0.... ..."
Table 11. Event Table for oWatchDogTimer
"... In PAGE 8: ...8 Table11 defines a function to strobe the watchdog timer when no fault has been detected. The first row states that oWatchDogTimer is set to true when it has remained false for 0.... ..."
Table 1: Latency of timer operations
1993
"... In PAGE 4: ...1 Timer operations We measured a series of microbenchmarks to evaluate the execution cost of each new timer operation. These measurements were repeated 1000 times and the average taken (controlling for clock and watchdog interrupts and their effect on the cache, the variance was very small) Table1 summarizes the latency of the timer operations. The measurements of timer arm() are best case numbers in which there are no pending timers earlier in the clock queue.... ..."
Cited by 8
Table 1: Latency of timer operations
1993
"... In PAGE 4: ...1 Timer operations We measured a series of microbenchmarks to evaluate the execution cost of each new timer operation. These measurements were repeated 1000 times and the average taken (controlling for clock and watchdog interrupts and their effect on the cache, the variance was very small) Table1 summarizes the latency of the timer operations. The measurements of timer arm() are best case numbers in which there are no pending timers earlier in the clock queue.... ..."
Cited by 8
Table 1: Latency of timer operations
1993
"... In PAGE 4: ...1 Timer operations We measured a series of microbenchmarks to evaluate the execution cost of each new timer operation. These measurements were repeated 1000 times and the average taken (controlling for clock and watchdog interrupts and their effect on the cache, the variance was very small) Table1 summarizes the latency of the timer operations. The measurements of timer arm() are best case numbers in which there are no pending timers earlier in the clock queue.... ..."
Cited by 8
Table 2 shows the specifications and major feature of the three custom designed boards in VuMan 3: main processor board, the PCMCIA controller board, and the docking station board, which acts as an input/output processor. A smart docking station monitors the use of the NiCd rechargeable batteries and also acts as a communication link to a logistic computer system, in order to upload the inspection data. Using the data in Table 1 the overhead factor for Navigator 1 is calculated as 56.5%, and for VuMan 3 as 5.6%
1998
"... In PAGE 6: ...3V @ 1.0 A PCMCIA Controller Board - 82365SL PCIC Chip - four buffers - 82365SL PCIC Chip - four buffers +5V@ current not specified Dock-ing Station Board - 8-bit D/A Converter - 8-bit A/D Converter - PIC Microcontroller - Watchdog timer - Powersaving Sleep Mode - 8-bit D/A Converter - 8-bit A/D Converter - PIC Microcontroller - Watchdog timer - Powersaving Sleep Mode +5V @ current not specified Table2 . Specifications of Custom Boards used in Navigator 1 Campus Tour Application, and miscellaneous data.... ..."
Cited by 6
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