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5,241
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
Abstract

Cited by 527 (44 self)
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, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.
Elementary Gates for Quantum Computation
, 1995
"... We show that a set of gates that consists of all onebit quantum gates (U(2)) and the twobit exclusiveor gate (that maps Boolean values (x, y)to(x, x⊕y)) is universal in the sense that all unitary operations on arbitrarily many bits n (U(2 n)) can be expressed as compositions of these gates. We in ..."
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Cited by 280 (11 self)
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investigate the number of the above gates required to implement other gates, such as generalized DeutschToffoli gates, that apply a specific U(2) transformation to one input bit if and only if the logical AND of all remaining input bits is satisfied. These gates play a central role in many proposed
Algebraic methods in the theory of lower bounds for boolean circuit complexity
 IN PROCEEDINGS OF THE 19TH ANNUAL ACM SYMPOSIUM ON THEORY OF COMPUTING, STOC ’87
, 1987
"... We use algebraic methods to get lower bounds for complexity of different functions based on constant depth unbounded fanin circuits with the given set of basic operations. In particular, we prove that depth k circuits with gates NOT, OR and MOD, where p is a prime require Ezp(O(n’)) gates to calcu ..."
Abstract

Cited by 329 (1 self)
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We use algebraic methods to get lower bounds for complexity of different functions based on constant depth unbounded fanin circuits with the given set of basic operations. In particular, we prove that depth k circuits with gates NOT, OR and MOD, where p is a prime require Ezp(O(n’)) gates
ARSMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
, 1999
"... This paper speculates that technology trends pose new challenges for fault tolerance in microprocessors. Specifically, severely reduced design tolerances implied by gigaherz clock rates may result in frequent and arbitrary transient faults. We suggest that existing faulttolerant techniques  syste ..."
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Cited by 246 (8 self)
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 systemlevel, gatelevel, or componentspecific approaches  are either too costly for general purpose computing, overly intrusive to the design, or insufficient for covering arbitrary logic faults. An approach in which the microarchitecture itself provides fault tolerance is required. We propose a new
Modelchecking algorithms for continuoustime Markov chains
 IEEE TRANSACTIONS ON SOFTWARE ENGINEERING
, 2003
"... Continuoustime Markov chains (CTMCs) have been widely used to determine system performance and dependability characteristics. Their analysis most often concerns the computation of steadystate and transientstate probabilities. This paper introduces a branching temporal logic for expressing realt ..."
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Cited by 235 (48 self)
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steadystate probabilities. We show that the model checking problem for this logic reduces to a system of linear equations (for unbounded until and the steadystate operator) and a Volterra integral equation system (for timebounded until). We then show that the problem of modelchecking timebounded
FLogic: A HigherOrder Language for Reasoning about Objects, Inheritance and Scheme
 ACM SIGMOD
, 1989
"... All intext references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately. ..."
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Cited by 194 (9 self)
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All intext references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.
Generalized Symbolic Execution for Model Checking and Testing
, 2003
"... Modern software systems, which often are concurrent and manipulate complex data structures must be extremely reliable. We present a novel framework based on symbolic execution, for automated checking of such systems. We provide a twofold generalization of traditional symbolic execution based ap ..."
Abstract

Cited by 232 (52 self)
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preconditions (e.g., acyclicity), data (e.g., integers and strings) and concurrency. The program instrumentation enables a model checker to automatically explore dierent program heap con gurations and manipulate logical formulae on program data (using a decision procedure). We illustrate two applications
Petrify: a tool for manipulating concurrent specifications and . . .
"... Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) 1 it (1) generates another PN or STG which is simpler than the original descripti ..."
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Cited by 219 (34 self)
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State Coding problem. State assignment is coupled with logic minimization and speedindependent technology mapping to a target library. The final netlist is guaranteed to be speedindependent, i.e., hazardfree under any distribution of gate delays and multiple input changes satisfying the initial
Noninteractive Private Auctions
, 2001
"... We describe a new auction protocol that enjoys the following properties: the biddings are submitted noninteractively and no information beyond the result is disclosed. The protocol is efficient for a logarithmic number of players. Our solution uses a semitrusted third party T who learns no informa ..."
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Cited by 44 (1 self)
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circuit evaluation by taking into account the level of each gate and allowing efficient computation of unbounded logical gates. In a scenario with a small numbers of players, we believe that our work may be of practical significance, especially for electronic transactions.
Firstorder incremental blockbased statistical timing analysis
 In DAC
, 2004
"... Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel lineartime blockbased statistical timing algorithm is emplo ..."
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Cited by 193 (6 self)
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enumeration programs. Numerical results are presented on industrial ASIC chips with over two million logic gates. 1.
Results 1  10
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