Results 1  10
of
2,649
Average Case Complexity of Unbounded Fanin Circuits
 Proc. 15th Conference on Computational Complexity (CCC
, 2000
"... Several authors have shown that the PARITYfunction cannot be computed by unbounded fanin circuits of small depth and polynomial size. Even more, constant depth k circuits of size exp(n \Theta(1=k) ) give wrong results for PARITY for almost half of all inputs. We generalize these results in two di ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
Several authors have shown that the PARITYfunction cannot be computed by unbounded fanin circuits of small depth and polynomial size. Even more, constant depth k circuits of size exp(n \Theta(1=k) ) give wrong results for PARITY for almost half of all inputs. We generalize these results in two
Depth Reduction for Circuits of Unbounded FanIn
, 1991
"... We prove that constant depth circuits of size n over the basis AND, OR, PARITY are no more powerful than circuits of this size with depth four. Similar techniques are used to obtain several other depth reduction theorems; in particular, we show every set in AC can be recognized by a family of ..."
Abstract

Cited by 19 (6 self)
 Add to MetaCart
We prove that constant depth circuits of size n over the basis AND, OR, PARITY are no more powerful than circuits of this size with depth four. Similar techniques are used to obtain several other depth reduction theorems; in particular, we show every set in AC can be recognized by a family of depth three . The size bound n is optimal when considering depth reduction over AND, OR, and PARITY. Most of our results hold both for the uniform and the nonuniform case.
Unambiguous Auxiliary Pushdown Automata And SemiUnbounded FanIn Circuits
, 1995
"... Notions of unambiguity for uniform circuits and AuxPDAs are studied and related to each other. In particular, a coincidence for counting and unambiguous versions of AuxPDAs and semiunbounded fanin circuits is shown. Moreover, an improved simulation of LOGUCFL (the class of languages logspace many ..."
Abstract

Cited by 19 (4 self)
 Add to MetaCart
Notions of unambiguity for uniform circuits and AuxPDAs are studied and related to each other. In particular, a coincidence for counting and unambiguous versions of AuxPDAs and semiunbounded fanin circuits is shown. Moreover, an improved simulation of LOGUCFL (the class of languages logspace many
Depth Lower Bounds for Monotone SemiUnbounded Fanin Circuits
, 2000
"... The depth hierarchy results for monotone circuits of Raz and McKenzie [6] are extended to the case of monotone circuits of semiunbounded fanin. It follows that the inclusions NC i SAC i AC i are proper in the monotone setting, for every i 1. 1 Introduction We consider boolean circuits ov ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
The depth hierarchy results for monotone circuits of Raz and McKenzie [6] are extended to the case of monotone circuits of semiunbounded fanin. It follows that the inclusions NC i SAC i AC i are proper in the monotone setting, for every i 1. 1 Introduction We consider boolean circuits
Algebraic methods in the theory of lower bounds for boolean circuit complexity
 In Proceedings of the 19th Annual ACM Symposium on Theory of Computing, STOC ’87
, 1987
"... kbstr act We use algebraic methods to get lower bounds for complexity of different functions based on constant depth unbounded fanin circuits with the given set of basic operations. In particular, we prove that depth k circuits with gates NOT, OR and MOD, where p is a prime require Ezp(O(n’)) gates ..."
Abstract

Cited by 331 (1 self)
 Add to MetaCart
kbstr act We use algebraic methods to get lower bounds for complexity of different functions based on constant depth unbounded fanin circuits with the given set of basic operations. In particular, we prove that depth k circuits with gates NOT, OR and MOD, where p is a prime require Ezp
Monotone Complexity
, 1990
"... We give a general complexity classification scheme for monotone computation, including monotone spacebounded and Turing machine models not previously considered. We propose monotone complexity classes including mAC i , mNC i , mLOGCFL, mBWBP , mL, mNL, mP , mBPP and mNP . We define a simple ..."
Abstract

Cited by 2837 (11 self)
 Add to MetaCart
We give a general complexity classification scheme for monotone computation, including monotone spacebounded and Turing machine models not previously considered. We propose monotone complexity classes including mAC i , mNC i , mLOGCFL, mBWBP , mL, mNL, mP , mBPP and mNP . We define a simple notion of monotone reducibility and exhibit complete problems. This provides a framework for stating existing results and asking new questions. We show that mNL (monotone nondeterministic logspace) is not closed under complementation, in contrast to Immerman's and Szelepcs 'enyi's nonmonotone result [Imm88, Sze87] that NL = coNL; this is a simple extension of the monotone circuit depth lower bound of Karchmer and Wigderson [KW90] for stconnectivity. We also consider mBWBP (monotone bounded width branching programs) and study the question of whether mBWBP is properly contained in mNC 1 , motivated by Barrington's result [Bar89] that BWBP = NC 1 . Although we cannot answer t...
Efficient implementation of a BDD package
 In Proceedings of the 27th ACM/IEEE conference on Design autamation
, 1991
"... Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
Abstract

Cited by 500 (9 self)
 Add to MetaCart
Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementation of the ifthenelse (ITE) operator. A hash table is used to maintain a strong carwnical form in the ROBDD, and memory use is improved by merging the hash table and the ROBDD into a hybrid data structure. A memory funcfion for the recursive ITE algorithm is implemented using a hashbased cache to decrease memory use. Memory function efficiency is improved by using rules that detect. when equivalent functions are computed. The usefulness of the package is enhanced by an automatic and lowcost scheme for rec:ycling memory. Experimental results are given to demonstrate why various implementation tradeoffs were made. These results indicate that the package described here is significantly faster and more memoryefficient than other ROBDD implementations described in the literature. 1
SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
Abstract

Cited by 514 (41 self)
 Add to MetaCart
SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII [5] and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.
Algorithms for Scalable Synchronization on SharedMemory Multiprocessors
 ACM Transactions on Computer Systems
, 1991
"... Busywait techniques are heavily used for mutual exclusion and barrier synchronization in sharedmemory parallel programs. Unfortunately, typical implementations of busywaiting tend to produce large amounts of memory and interconnect contention, introducing performance bottlenecks that become marke ..."
Abstract

Cited by 567 (32 self)
 Add to MetaCart
Busywait techniques are heavily used for mutual exclusion and barrier synchronization in sharedmemory parallel programs. Unfortunately, typical implementations of busywaiting tend to produce large amounts of memory and interconnect contention, introducing performance bottlenecks that become markedly more pronounced as applications scale. We argue that this problem is not fundamental, and that one can in fact construct busywait synchronization algorithms that induce no memory or interconnect contention. The key to these algorithms is for every processor to spin on separate locallyaccessible ag variables, and for some other processor to terminate the spin with a single remote write operation at an appropriate time. Flag variables may be locallyaccessible as a result of coherent caching, or by virtue of allocation in the local portion of physically distributed shared memory. We present a new scalable algorithm for spin locks that generates O(1) remote references per lock acquisition, independent of the number of processors attempting to acquire the lock. Our algorithm provides reasonable latency in the absence of contention, requires only a constant amount of space per lock, and requires no hardware support other than
Results 1  10
of
2,649