• Documents
  • Authors
  • Tables
  • Log in
  • Sign up
  • MetaCart
  • DMCA
  • Donate

CiteSeerX logo

Advanced Search Include Citations

Tools

Sorted by:
Try your query at:
Semantic Scholar Scholar Academic
Google Bing DBLP
Results 1 - 10 of 18,785
Next 10 →

Experimental Study of Scan-Based Transition Fault Testing Techniques

by Vinay B. Jayaram, Vinay B. Jayaram , 2003
"... The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault ..."
Abstract - Add to MetaCart
The presence of delay-inducing defects is causing increasing concern in the semiconductor industry today. To test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition

At-Speed Transition Fault Testing With Low Speed Scan Enable

by Nisar Ahmed, C. P. Ravikumar - in proc. IEEE VLSI Test Symposium (VTS’05 , 2005
"... With today’s design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launchoff-shift method has several advantages over the launch-offcapture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan- ..."
Abstract - Cited by 10 (5 self) - Add to MetaCart
With today’s design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launchoff-shift method has several advantages over the launch-offcapture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan

Abstract Deterministic Logic BIST for Transition Fault Testing 1

by Valentin Gherman, Hans-joachim Wunderlich
"... BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLB ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification has been used to generate the required pattern pairs. The efficiency of the extended scheme is investigated using

1At-Speed Transition Fault Testing With Low Speed Scan Enable

by Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
"... With today’s design size in millions of gates and working fre-quency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault test-ing due to at-speed scan enable signal. A novel s ..."
Abstract - Add to MetaCart
With today’s design size in millions of gates and working fre-quency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault test-ing due to at-speed scan enable signal. A novel

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis

by U Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-tung Cheng, Alex Babin, Kun-han Tsai, Nagesh Tamarapalli, Greg Aldrich
"... As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during Automatic Test Pattern Generation (ATPG), it is possible ..."
Abstract - Add to MetaCart
in the speed of the transition fault test pattern. However, occasionally we did find some failing paths were real functional problems and design changes were needed to resolve them.

Diagnosing multiple faults.

by Johan De Kleer , Brian C Williams - Artificial Intelligence, , 1987
"... Abstract Diagnostic tasks require determining the differences between a model of an artifact and the artifact itself. The differences between the manifested behavior of the artifact and the predicted behavior of the model guide the search for the differences between the artifact and its model. The ..."
Abstract - Cited by 808 (62 self) - Add to MetaCart
. The diagnostic procedure presented in this paper is model-based, inferring the behavior of the composite device from knowledge of the structure and function of the individual components comprising the device. The system (GDE -General Diagnostic Engine) has been implemented and tested on many examples

Bisimulation through probabilistic testing

by Kim G. Larsen, Arne Skou - in “Conference Record of the 16th ACM Symposium on Principles of Programming Languages (POPL , 1989
"... We propose a language for testing concurrent processes and examine its strength in terms of the processes that are distinguished by a test. By using probabilistic transition systems as the underlying semantic model, we show how a testing algorithm can distinguish, with a probability arbitrarily clos ..."
Abstract - Cited by 529 (14 self) - Add to MetaCart
We propose a language for testing concurrent processes and examine its strength in terms of the processes that are distinguished by a test. By using probabilistic transition systems as the underlying semantic model, we show how a testing algorithm can distinguish, with a probability arbitrarily

Selected best papers from ETS’06 Deterministic logic BIST for transition fault testing

by V. Gherman, H. -j. Wunderlich, J. Schloeffel, M. Garbers
"... 1 ..."
Abstract - Add to MetaCart
Abstract not found

SIS: A System for Sequential Circuit Synthesis

by Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, Alberto Sangiovanni-Vincentelli , 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output b ..."
Abstract - Cited by 527 (44 self) - Add to MetaCart
as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation

Experimental Estimates of Education Production Functions

by Alan B. Krueger - Princeton University, Industrial Relations Section Working Paper No. 379 , 1997
"... This paper analyzes data on 11,600 students and their teachers who were randomly assigned to different size classes from kindergarten through third grade. Statistical methods are used to adjust for nonrandom attrition and transitions between classes. The main conclusions are (1) on average, performa ..."
Abstract - Cited by 529 (19 self) - Add to MetaCart
This paper analyzes data on 11,600 students and their teachers who were randomly assigned to different size classes from kindergarten through third grade. Statistical methods are used to adjust for nonrandom attrition and transitions between classes. The main conclusions are (1) on average
Next 10 →
Results 1 - 10 of 18,785
Powered by: Apache Solr
  • About CiteSeerX
  • Submit and Index Documents
  • Privacy Policy
  • Help
  • Data
  • Source
  • Contact Us

Developed at and hosted by The College of Information Sciences and Technology

© 2007-2019 The Pennsylvania State University