Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multicontext

by sequentially executing the instructions that describe it. Three independent execution units and a two-level memory hierarchy offer high emulation performance. FPGA-based logic emulators are capacity-limited by the low gate density on FPGAs and typically achieve no more than 25% logic block utilization due

Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time-multiplexing makes it possible to reduce the size of FPGA’s but requires a new step in the design

reconfigured from their internal configuration memories by means of a fast context swapping. Their very fast reconfiguration time permits mapping virtual circuits efficiently, that is, a time-multiplexed execution of circuit partitions that behaves as the circuit statically implemented on a larger capacity

for Reconfigurable Execution), a streambased compute model which virtualizes reconfigurable computing resources (compute, storage, and communication) by dividing a computation up into fixed-size "pages" and time-multiplexing the virtual pages on available physical hardware. Consequently, SCORE applications

. The static schedule makes the NoC timepredictable and enables worst-case execution time analysis of communicating real-time tasks. Keywords-real-time systems; network-on-chip I.

In a multithreaded execution, each thread can be thought of as running on its own virtual processor, with several virtual processors multiplexed onto a single physical processor. At any given time, some of these virtual processors are either sending or waiting for messages. When the degree

Abstract—A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect are time-multiplexed. Thus, for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper

configuration planes, context-switching overhead, and the end-user application are examined as we map the algorithm onto this architecture. Background Unless an algorithm mapped to hardware can be fully pipelined, some of the hardware will be idle during the execution of the algorithm. A time-multiplexed FPGA

proportional sharing across all real-time and conventional tasks. Furthermore, when not all real-time constraints can be met, SMART satisfies each real-time task's proportional share of deadlines, and adjusts its execution rate dynamically. This technique is especially important for multimedia