### Table 2: Experiment result for MCNC benchmarks Benchmark Without thermal constraints With thermal constraints

"... In PAGE 5: ...5. Table2 shows the experimental results for 8 test cases. The results from the runs with and without thermal con-... ..."

### TABLE I AREA/WIRE-DRIVEN VS THERMAL-DRIVEN VS AREA/WIRE-DRIVEN UNDER THERMAL CONSTRAINT. ckts

### Table 4. Correlation between the difference between the given thermal constraint and the maximum temperature for a test session, test time and simulation effort

in Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling

"... In PAGE 7: ...52 muresan 20 150 N/A N/A N/A muresan 20 130 N/A N/A N/A Table 3. Thermal-safe test schedule with fixed shift frequency for muresan 20 Table4 reports a more detailed set of simulation results for the designs muresan 20 and system l. For each design (column 1) and thermal constraint (column 2), different values for the allowed dif- ference between the thermal contraint Tmax and the final maximal temperature for each test session MaxTemp(TS) (see Figure 1) were chosen (column 3).... ..."

### Table 3. Thermal Stress Induced 90 Crack Density of [+q n/-q n/902n]s constraint ply angle

"... In PAGE 20: ... It was certain that they were not a result of cutting individual specimens, as was verified by marking the location of each crack on each specimen and piecing the panels together again to see that cracks were continuous from one specimen to the next. A summary of the thermal stress-induced crack density in the 90 plies of each [+q n/-q n/902n]s laminate is given in Table3 . In the columns labeled r the crack spacing a is divided by the thickness, d, of the 90 ply block.... ..."

### Table 2 Change in cutsize and standard deviation for the benchmark circuits simulated with SIS.

2003

"... In PAGE 5: ... Table2 shows the improvement in the standard deviation and deterioration of cutsize as the thermal constraints were tightened for circuits whose power information is from SIS. In the randomly generated circuits, skew values of 50 and 25 did not affect the number of cells and nets were larger and were not affected by the thermal constraints until the skew was as tight as it can get.... ..."

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### Table 1: Comparison of the P/G networks design with and without thermal integrity.

"... In PAGE 7: ...ound of the self-consistent current density, e.g., 5:5mA= m2 to avoid high current density wires. This can be observed in Table1 for the case with thermal-aware design that wire rms current density is in the region 3:58 5:5mA= m2. For the case without thermal integrity, the EM constraint gives the target rms current density 5:5mA= m2.... ..."

### Table 6: Comparisons of via distribution at di erent levels.

"... In PAGE 6: ...3 Comparison between Sequential and Simultaneous Optimizations We further compare the sequential optimization with the simul- taneous thermal/power optimization, and rst discuss via pat- terns for thermal and power integrity, respectively. As shown in Table6 , for a circuit with 27740 tiles, when only using the thermal-constraint, more vias tend to be stapled for high-level patterns. As a higher level pattern means more uniform via dis- tribution, the thermal constraint results in a more uniformly dis- tributed via pattern.... ..."

### Table 1. Comparison of the P/G networks design with and without thermal integrity.

2004

"... In PAGE 5: ... Due to the prac- tical concerns as discussed, an upper bound of current den- sity jub = 7:5mA= m2 is given to avoid high current den- sity wires. This can be observed in Table1 for the case with thermal integrity that wire rms current density is in the re- gion 3:6 7:5mA= m2. For the case without thermal in- tegrity, the EM constraint gives the target rms current density 7:5mA= m2.... ..."

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### Table 4: Worst set of uncertainties obtained for the uncertainty-based optimum for each constraint for the SMA microgripper problem.

"... In PAGE 8: ...e. largest) constraint values for the final design are listed in Table4 for all four constraints. For the temperature constraints, only the uncertainties in the thermal quantities are meaningful, and their worst case values match theoretical predictions.... ..."

### Table 1. The thermal profile of the RPM required to meet the IDR CGR of 40% for different platter- sizes. We assume a single-platter disk with nzones = 50 and a 3.5 form-factor enclosure. The thermal envelope is 45.22 C.

2005

"... In PAGE 7: ... In the absence of any thermal constraints, if we are to meet the IDR target for a given year, we would use the largest platter size possible and merely modulate the RPM to reach the desired value (step 2 of the method). Table1 gives the RPM that is required in each year for the three platter sizes that we consider and the steady state temperature that is reached for a one platter configu- ration. Trends for 2 and 4 platter configurations are similar, and are not explicitly shown here.... In PAGE 7: ... For example, consider the year 2005. From Table1 , we no- tice that a speed of 30,367 RPM would be required to meet the IDR for the 2.1 size.... In PAGE 10: ...6 size and be able to satisfy the 40% IDR CGR till the year 2005. From Table1 , we find that this needs an RPM of 24,534. Let us assume that we would like to build a disk which operates at this RPM even though in the worst case it would violate the thermal envelope and heat up to 48.... ..."

Cited by 14